br2cr  br2cr  br2cr  sc2mod0  sc2mod0  sc2cr  transmit counter (16 for uart) receive counter (16 for uart) receive control serial channel  interrupt control transmit control sc2mod0  receive buffer 1  (shift register) parity control receive buffer 2 (sc2buf) sc2cr  error flag transmit buffer 1 (shift register) transmit buffer 2 (sc2buf) sc2cr  sc2cr    sc2cr  sc2mod0  imclk sclk2 input (shared with  p87) sclk2 output (shared with  p87) rx2 (shared with  p85) tx2 (shared with  p86) cts2 (shared with  p87) interrupt request intrx2 interrupt request inttx2 sioclk txdclk rxdclk sc2mod0  receive fifo im-bus receive control transmit fifo transmit control  fifo interrupt control  interrupt request intrx2 interrupt request inttx2 sc2fr c  sc2ftc  sc2frc   sc2ftc   sc2frc  sc2ftc  to serial channel  interrupt control   figure 12.2.1   sio2 block diagram      tmp19a71   12-2 

 tmp19a71        12.3  sio components (sio2)  12.3.1 prescaler  the sio2 has a 7-bit prescaler that slows the ra te of a clocking source to the serial clock  generator. the prescaler clock source (imclk ) can be programmed in the prs2 bit of the  clkprsc located within the clock generator.   the prescaler can output four types of cloc ks to the baud rate gen erator: imclk/2,  imclk/8  imclk/32 and imclk/128.  the serial clock is selectable from several clocks; the prescaler is only enabled when the  baud rat e generator output clock is  selected as a serial clock.  table 12.3.1  shows prescaler  outp ut clock resolutions.    table 12.3.1 prescaler output clock resolutions     fc = 12 mhz (pll output clock)  prescaler output clock resolution  clock gear value  clkprsc.prs1  imclk selection  clkpsc.prs2   imclk/2 imclk/8  imclk/32  imclk/128  000 (fsys/2)  fc/8 (71.4 ns)  fc/32 (0.29   s)  fc/128 (1.1   s)  fc/512 (4.6   s)   010 (fsys/3)  fc/12 (107 ns)  fc/48 (0.43   s)  fc/192 (1.7   s)  fc/768 (6.9   s)   100 (fsys/4)  fc/16 (143 ns)  fc/64 (0.57   s)  fc/256 (2.3   s)  fc/1024 (9.1   s)  00 (fc/2)  110 (fsys/5)  fc/20 (178 ns)  fc/80 (0.71   s)  fc/320 (2.9   s)  fc/1280 (11.4   s) 000 (fsys/2)  fc/16 (143 ns)  fc/64 (0.57   s)  fc/256 (2.3   s)  fc/1024 (9.1   s)  010 (fsys/3)  fc/24 (187 ns)  fc/96 (0.86   s)  fc/384 (3.4   s)  fc/1524 (13.7   s) 100 (fsys/4)  fc/32 (286 ns)  fc/128 (1.1   s)  fc/512 (4.6   s)  fc/2048 (18.3   s) 01 (fc/4)  110 (fsys/5)  fc/40 (357 ns)  fc/160 (1.43   s) fc/640 (5.7   s)  fc/2560 (22.9   s) 000 (fsys/2)  fc/32 (0.29   s)  fc/128 (1.1   s)  fc/512 (4.6   s)  fc/2048 (18.3   s) 010 (fsys/3)  fc/48 (0.43   s)  fc/192 (1.7   s)  fc/768 (6.9   s)  fc/3048 (17.4   s) 100 (fsys/4)  fc/64 (0.57   s)  fc/256 (2.3   s)  fc/1024 (9.1   s)   fc/4096 (36.6   s) 10 (fc/8)  110 (fsys/5)  fc/80 (0.71  s)  fc/320 (2.9   s)  fc/1280 (11.4   s)   fc/5120 (45.8   s) note: do not change the clock gear value while the sio is operating.           tmp19a71   12-3 

 tmp19a71          12.3.2  baud rate generator  the frequency used to transmit and receiv e data through the sio2 is derived from  the baud rate generator. the clock source for the baud rate generator can be selected  from the 7-bit prescaler outputs (imc lk/2, imclk/8, imclk/32, imclk/128)  through the programming of the pre bit in the br2cr.     the baud rate generator contains a clock di vi der that can divide the selected clock  by n (n = 1 to 16) or n+(16-k)/16 ( n = 2  to 15, k = 1 to 15). the clock divisor is  programmed into the dvs and br2s bits in  the br2cr and the br2k bit in the  br2add.     i/o interface mode   ?     i/o interface mode cannot utilize the n  +  (16  ?   k)/16 clock division function.  the  dvs bit in the br2cr must be cleared to 0.     uart mode   ?     1) when br2cr.dvs = 0  when the br2cr.dvs bit is cleared, the br2add.br2k field has no meaning  or effect. in  this case, the baud rate ge nerator input clock is divided down by a  value of n (1 to 16) programmed in the br2cr.br2s field.   2) when br2cr.dvs = 1  setting the br2cr.dvs bit to 1 enables the n  +  (16  ?  k)/16 division function.  the baud rate generator input clock is di vided down according to the value of n  (2 to 15) programmed in the br2cr.br2s field and the value of k (1 to 15)  programmed in the br2add.br2k field.   note:  setting n to 1 or 16 disables the n  +  (16  k)/16 clock division function. when n = 1 or 16, the  br2cr.dvs bit must be cleared to 0.       baud rate calculations     1)   i/o inter face mode    ba ud rate  =             2  bau ?                   when the clock input to the baud rate benerator is imclk/2 (14 mhz) and the  baud rat e generator divisor is set to 2, the maximum baud rate is 3.5 mbps. baud rate generator input clock  d  rate generator divisor    tmp19a71   12-4 

 tmp19a71          2)   uart mode     baud rate  =               16                  when the clock input to the baud rate generator is imclk/2 (14 mhz), the  maxi mum baud rate is 875 kbps.   the baud rate generator can be bypassed if the user wants to use the imclk  clock as a serial clock. in  this case , the maximum baud rate is 1.75 mbps (at  imclk = 28 mhz).     baud rate generator input clock  r divisor  baud rate generato calculation examples     ?   1)   integra l division (divide-by-n)  imclk  =  28  mhz  baud rate generator input clock: imclk/8  clock divisor n (br2cr.br2s)  =  4  br2cr.dvs  =  0      clocking conditions  system clock  : 56 mhz     im clk    : 28 mhz (divide-by-2)  (16-5) 16  5  +   imclk/32     16   baud rate  =   4 imclk/8     16  =  28    10 6     8    4    16  =  54.7  kbps)    note:  clearing the br2cr.dvs bit to 0 disables the n +  (16 - k)/16 clock division function. at this time, the  br2add.br2k field is ignored.       2)   n  +  (16 - k )/16 clock division (uart mode only)  imclk  =  28  mhz  baud rate generator input clock: imclk/32  n (br2cr.br2s)  =  5  k (br2add.br2k)  =  5  br2cr.dvs  =  1      clocking conditions  system clock  : 56 mhz      im clk  : 28 mhz (divide-by-2)     baud rate   =        =  28    10 6     32    (5  +      )    16  =  9615 (bps)    11 16       tmp19a71   12-5 

 tmp19a71            the sio2 can use an external clock as a  se rial clock, bypassing the baud rate  generator. when an external clock is us ed, the baud rate is determined as shown  below.     using an external clock as a serial clock   ?     1)   i/o inter face mode  baud rate = external clock input   when double-buffering is used, the external clock period must be greater than  12/ fsys. therefore, when fsys = 56 mhz,  the maximum baud rate is 4.7 mbps (56   12).   when double-buffering is not used, the  e xernal clock period must be greater  than 16/fsys. therefore, when fsys = 56  mhz, the maximum baud rate is 3.5 mbps  (56  16).     2)   uart mode  baud rate   =   external clock input     16  the external clock input must be greater than or equal to 4/fsys. therefore,  when  fsys = 56 mhz, the maximum baud rate is 875 kbps (56  4  16).  table 12.3.2  and  table 12.3.3  show baud rate setting examples in uart mode.    tmp19a71   12-6 

 tmp19a71        table 12.3.2   uart baud rate selection  logic baud rate (bps)  generated baud rate (bps) prescaler  divisor n  correction  value     error (%) 1200 1202  imclk/128  11  10  0.16  2400 2404  imclk/128  5  5  0.16  4800 4808  imclk/32  11  10  0.16  9600 9615  imclk/32  5  5  0.16  14400 14403  imclk/8  15  13  0.02  19200 19231  imclk/8  11  10  0.16  28800 28689  imclk/8  7  6  0.39  31250 31250  imclk/8  7  none  0  38400 38462  imclk/8  5  5  0.16  57600 57613  imclk/2  15  13  0.02  115200 115702  imclk/2  7  7  0.44  230400 229508  imclk/2  3  3  0.39  note 1:  this table assumes: fsys = 56 mhz,  imclk = fsys/2 (28 mhz).  note 2:  when a baud rate slower than 600 bps is used, the input clock must be tmrb2.       table 12.3.3   ua rt baud rate selection  tb2reg1 values when the tmrb2 timer trigger output (internal tb2out) is used  (tmrb2 input clock = imclk/4)    imclk    baud rate  (bps)  28 mhz  20 mhz  14 mhz  10 mhz  7 mhz  100 4375  3125 2188 1563  1094  150 2916  2084 1458 1042  730  200  2188 1563  1094  781  547  300  1458 1042  729  521  365  400  1094  781 547 391  273  500  875  625 438 313  219  600  729  521 365 260  182    when the timer tmrb2 is used to generate a seri al cloc k, the baud rate is determined by the  following equation:              baud rate  =     imclk  tb2reg1   4   16 (when the tmrb2 clock source is imclk/4)    note:  in i/o interface mode, the sio2 and sio3 cannot utilize the trigger output signal (internal) from the timer  tmrb2 as a serial clock.    tmp19a71   12-7 

 tmp19a71          12.3.3  serial clock generator  this block generates a basic clock that cont rols the transmit and receive operations.    i/o interface mode   if the sclk2 pin is configured as an output by clearing the sc2cr.ioc bit to 0,  the o utput clock from the baud rate generator is divided by two to generate the basic  clock.   if the sclk2 pin is configured as an inpu t by sett ing the sc2cr.ioc bit to 1, the  external sclk2 clock is used as the basic clock; the sc2cr.sclks bit determines  the active clock edge.   ?     uart mode   the basic clock (sioclk) is selected from a clock produced by the baud rate  gen erator, the system clock (imclk/2), the internal output signal from the timer  tmrb2, and the external sclk2 clock, according to the setting of the  sc2mod0.sc field.   ?     12.3.4 receive counter  the receive counter is a 4-bit binary up-counter used in uart mode. this counter is  clocked by sioclk. the receiver utilizes 16 clocks for each received bit, and oversamples  each bit three times around their center (with 7th to 9th clocks). the value of a bit is  determined by voting logic which takes the  value of the majority of three samples.     12.3.5 receive controller  i/o interface mode   if the sclk2 pin is configured as an outp ut b y clearing the sc2cr.ioc bit to 0,  the receive controller samples the rx2 input at the rising edge of the shift clock  driven out from the sclk2 pin.   if the sclk2 pin is configured as an inpu t by sett ing the sc2cr.ioc bit to 1, the  receive controller samples the rx2 input at either the rising or falling edge of the  sclk2 clock, as programmed in the sc2cr.sclks bit.   ?     uart mode   the receive controller uses 16 clocks for re ceivin g the start bit. it samples the 7th  to 9th clocks to determine by voting logic whether or not the correct start bit is  received. receive operation is started upon reception of the correct start bit.   ?     12.3.6 receive buffer  the receive buffer is double-buffered to  prevent overrun errors. received data is  serially shifted bit by bit into receive buffer 1. when a whole frame is loaded into  receive buffer 1, it is transferred to receive buffer 2 (sc2buf), and the intrx2 is  generated. at this time, the receive buffer  full flag (sc2mod2.rbfll) is set to 1,  indicatig that receive buffer 2 contains valid data.     the tx19a core processor reads a frame from receive buffer 2 (sc2buf), causing  the  receive buffer full flag (sc2mod2.rbfll)  to be cleared to 0. receive buffer 1    tmp19a71   12-8 

 tmp19a71        can accept a new frame before the tx19a co re processor picks up the previous frame  in receive buffer 2 (sc2buf).     if the sclk2 pin is configured as an output in i/o interface mode, receive buffer 2  (sc 2buf) can be enabled or disabled by programming the wbuf bit in the sc2mod2.   disabling receive buffer 2 (double-buffer ing) enables handshaking during data  transfer; the sio2 stops outputting the sclk2 clock every time a single frame has  been transmitted. in this case, the tx19a  core processor reads a frame from receive  buffer 1, causing the output of the sclk2 clock to be restarted. if receive buffer 2  (double-buffering) is enabled, a received frame is transferred from receive buffer 1 to  receive buffer 2. once a next frame is received resulting in both receive buffers 1 and  2 containing valid data, the sio2 stops outputting the sclk2 clock. when the tx19a  core processor reads a frame from receive buffer 2, the frame stored in receive buffer  1 is transferred to receive buffer 2, causing a receive-done interrupt (intrx2) to  occur and the sio2 to restart outputting the sclk2 clock. consequently, no overrun  error occurs if the sclk2 pin is configured as an output in i/o interface mode,  regardless of the setting of the sc2mod2.wbuf bit.     note:  in sclk output mode, the oeer flag in the sc2cr has no meaning; it is read as undefined. when  exiting sclk output mode, first read the sc2cr to initialize this flag.     in other operating modes, receive buffer 2 is always enabled to improve  per formance during continuous transfer.  however, the tx19a core processor must  read receive buffer 2 (sc2buf) before receive buffer 1 is filled with a new frame.  otherwise, an overrun error occurs, causing the frame previously stored in receive  buffer 1 to be lost. even in that case, the contents of receive buffer 2 and the  sc2cr.rb8 bit are preserved.     the sc2cr.rb8 bit holds the parity bit in 8-bit uart mode and the most  sign ificant bit in 9-bit uart mode.      in 9-bit uart mode, the receiver wake-up feature can be enabled for slave  contr ollers by setting the sc2mod0.wu bit  to 1. the receiver  generates the intrx2  interrupt only when the sc2cr.rb8 bit is set to 1.     tmp19a71   12-9 

 tmp19a71            12.3.7 transmit counter  the transmit counter is a 4-bit binary up -counter used in uart mode. like the  receive counter, the transmit counter is  also clocked by sioclk. the transmitter  generates a transmit clock (txdclk) pulse every 16 sioclk pulses.           sioclk  txdclk 15  16  1 2  4 5 67 8 910 11 12 13   14  15 16  3 1 2     figure 12.3.1   t ransmit clock generation      12.3.8 transmit controller    i/o interface mode ?     if the sclk2 pin is configured as an output by clearing the sc2cr.ioc bit to 0,  the tr ansmit controller shifts out each bit in the transmit buffer to the tx2 pin at  the falling edge of the shift clock driven out on the sclk2 pin.   if the sclk2 pin is configured as an inpu t by sett ing the sc2cr.ioc bit to 1, the  transmit controller shifts out each bit in the transmit buffer to the tx2 pin at either  the rising or falling edge of the sclk2 input, as programmed in the sc2cr.sclks  bit.     uart mode   once the tx19a core processor loads a frame into the transmit buffer, the  transmit controller begins transmission  a t the next falling edge of txdclk,  producing a transmit shift clock.  ?     tmp19a71   12-10 

 tmp19a71        handshaking (sio2 and sio3 only)   the sio2 has a clear-to-send (cts2) pin. if the cts operation is enabled, a frame  can be  transmitted only when the cts2 input is low. this feature can be used for flow  control to prevent overrun errors in the  receiver. the sc2mod0.ctse bit enables and  disables the cts operation.     if the cts2 pin goes high in the middle of a transmission, the transmit controller  stops tra nsmission upon completion of the current frame until cts2 goes low again. if  so enabled, the transmit controller generates the inttx2 interrupt to notify the  tx19a core processor that the transmit buffer is empty. after the next frame is loaded  into the transmit buffer, the transmit controller remains in an idle state until it  detects cts2 going low.     although the sio2 does not have the  rts  pin, any general-purpose port pins can  serve as the  rts  pin. the receiving device uses the  rts output to control the cts2  input of the transmitting device. once the receiving device has received a frame,  rts  should be set to high in the receive-done interrupt handler to temporarily stop  the transmitting device from sending the next frame. this way, the user can easily  implement a two-way handshake protocol.        rx2  rts2 (any port)  receiving device  transmitting device tx2  cts2 tmp19a71 tmp19a71                  figure 12.3.2   ha ndshaking signals                              3 2 16 1 15 start bit  bit 0  (1)  (2)  period  no transmission  during this   14 13   write to transmit buffer  cts2 14  15 16  1  2  3  sioclk txdclk tx2   note 1:  if the cts2 signal goes high in the middle of a transmission, the transmitter sotps transmission after the  current frame has been sent.  note 2:  the transmitter starts transmission at the first fa llin g edge of the txdclk clock after the cts2 signal goes  low.    figure 12.3.3   clear-to-send (cts) signal timing   tmp19a71   12-11 

 tmp19a71            12.3.9  generating a waveform with a 50% duty cycle  when the uart bit in the sc2mod1 is set  to 1, the uart output and the internal  transmit signal are ored, as shown in  figure 12.3.4 . when the baud rate generator divisor  is set to a v alue of n in uart mode, a waveform with a 50% duty cycle is generated. the  duty ratio varies when the n+ (16-k)/16 clock division function is used.                       figure 12.3.4  waveform generation wi th a 50% duty  cycle (divide-by-n)    uart output internal signal output with a 50% duty cycle 12.3.10  accuracy of waveform generation with a 50% duty cycle  (a)   when the baud rate generator di visor is set to a value of n  a waveform with a 50% duty cycle is generated.     (b)   whe n the n + (16 - k)/16 clock division function is used  the duty ratio is calculated as the ratio of low width to high width as shown below.   k = 0 to 8   : (k  n) +  8 - k)  (n + 1): 8  (n + 1)  k = 8 to 16  : 8  n: (k - 8)  n + (16 - k)  (n + 1)   the largest deviation occurs when k = 8 and n = 1. in this case, the ratio of low width  to high widt h is 8:16 (33%:67%).      example: generating 9600 bps by using the  n + (16 ? k)/16 clock division function  system clock : fsys = 56 mhz (imclk = 28 mhz)  input clock  : imclk/32 = 875 khz  baud rate  : 9615 bps (n = 5, k = 5)  duty ratio  : low:high = 43:48 = 47.25%:52.75%    tmp19a71   12-12 

 tmp19a71          12.3.11 transmit buffer  the transmit buffer is double-buffered. doub le-buffering can be enabled or disabled by  programming the wbuf bit in the sc2mod2. if  double-buffering is enabled, a frame is  first written to transmit buffer 2 (sc2buf) and then transferred to transmit buffer 1  (shift register), causing the inttx2 interrupt  to occur and the transmit buffer empty  flag (sc2mod2.tbemp) to be set. this flag indicates that transmit buffer 2 is empty  and a next transmit frame can be written.  writing a next frame to transmit buffer 2  clears the tbemp flag.   when the sclk2 pin is configured as an input in i/o interface mode, an underrun error  occurs upon  completion of transmitting a fram e from transmit buffer 1 if a next frame is  not written to transmit buffer 2 before the clock pulse for the next frame is input. an  underrun error is indicated by the parity/und errun flag (perr) in the sc2cr. when the  sclk2 pin is configured as an output in i/o  interface mode, the sio2 stops outputting the  sclk2 clock after transmitting a frame which  has been transferred from transmit buffer  2 to transmit buffer 1. in this mode, therefore, no underrun error occurs.     note:  when the sclk2 pin is configured as an output in i/o interface mode,  the perr flag in the sc2cr has  no meaning; it is read as undefined. when exiting sclk output mode, first read the sc2cr to initialize  this flag.     if double-buffering is disabled, the tx19a core processor writes a transmit frame to  transmit buffer 1. the inttx2 interrupt is generated upon completion of  transmission.   if handshaking is required, transmit buffer 2 must be disabled by clearing the wbuf  bit in t he sc2mod2. for continuous transmi ssion without handshaking, transmit buffer  2 can be enabled by setting the wbuf bit to improve performance. when double-buffering  is not used, do not write to transmit buffer 1 while a frame is being transmitted.     12.3.12 parity controller  for transmit operations, setting the sc2cr.pe  bit to 1 enables parity generation in 7-  and 8-bit uart modes. the sc2cr.even bit selects either even or odd parity.   if enabled, the parity controller automati cally generates parity for the frame in the  transm it buffer (sc2buf). in 7-bit uart  mode, the tb7 bit in the sc2buf holds the  parity bit. in 8-bit uart mode, the tb8 bit in the sc2mod holds the parity bit. the parity  bit is set after the frame has been transmitted. the sc2cr.pe and sc2cr.even bits  must be programmed prior to a write to the transmit buffer.  for receive operations, the pari t y controller automatically co mputes the expected parity  when a frame in receive buffer 1 is transferred to receive buffer 2 (sc2buf). the received  parity bit is compared to the sc2buf.rb7 bit in 7-bit uart mode and to the sc2cr.rb8  bit in 8-bit uart mode. if a frame is received  with incorrect parity, the sc2cr.perr bit is  set.  in i/o interface mode, the sc2cr.perr bit in dicates an under run error rather than a  parity error.           tmp19a71   12-13 

 tmp19a71          12.3.13 error flags  the sio2 has the following three error flags for improved data reception reliability.    1.  overrun error: sc2cr.oerr  in uart and i/o interface mode, an ove rrun err or is reported with the oerr  bit set to 1 if all bits of a new frame are  received before the current frame is read  from the receive buffer. reading the flag causes it to be cleared. note that an  overrun error can only be cleared by re ading the receive buffer or executing a  software reset using the sc2mod2.swrst.   when the sclk2 pin is configured as an  output in i/o interface mod e, however,  no overrun error occurs so that the oerr  flag has no meaning and is read as  undefined.     2.  parity error/underrun error: sc2cr.perr  in uart mode, this flag indicates wh et her a parity error has occurred. a  parity error is reported when the parity  bit attached to a received frame does not  match the expected parity computed from the frame. reading the flag causes it to  be cleared.   in i/o interface mode, this flag indicates whether an underrun error has  occurr ed, only when double-buffering (transmit buffer 2) is enabled  (sc2mod2.wbuf = 1) with the sclk2 pin configured as an input. an underrun  error is reported upon completion of transmitting a frame from transmit buffer 1  if a next frame is not written to transmit buffer 2 before the clock pulse for the  next frame is input. when the sclk2 pin  is configured as an output, no underrun  error occurs so that the perr flag na s no meaning and is read as undefined.  reading the flag causes it to be cleared.     3.   fr aming error: sc2cr.ferr  in uart mode, this flag indicates whether a framing error has occurred. a  fram ing error is reported if a 0 is detected where a stop bit was expected. (the  middle three of the 16 samples are used to determine the bit value.) reading the  flag causes it to be cleared. during reception, only a single stop bit is detected  regardless of the setting of the sblen bit in the sc2mod2.     tmp19a71   12-14 

 tmp19a71          table 12.3.4   error flags  operating mode  error flag  function  oerr  overrun error flag  perr  parity error flag  uart  ferr framing  er ror  flag  oerr  overrun error flag  underrun error flag (wbuf=1)  perr  fixed to 0 (wbuf=0)  i/o interface  (sclk  input)  ferr  fixed to 0  oerr undefined  perr undefined  i/o interface  (sclk output)  ferr  fixed to 0      12.3.14 bit transfer sequence  the drchg bit in serial mode control register 2 (sc2mod2) determines whether the  most significant bit (msb) or least significant  bit (lsb) is transmitted first in i/o interface  mode. the setting of the drchg bit cannot be mo dified while the sio is transferring data.     12.3.15  stop bit length  the sblen bit in the sc2mod2 determines the number of stop bits (1 or 2) used in  uart mode.       tmp19a71   12-15 

 tmp19a71            12.3.16 status flag  the rbfll bit in the sc2mod2 indicates whether receive buffer 2 is full when  double-buffering is enabled (sc2mod2.wbuf  =  1). it is set to 1 once a received frame  is transferred from receive buffer 1 to rece ive buffer 2. the rbfll bit is cleared to 0  when the tx19a core processor or dmac reads data from receive buffer 2. when  wbuf = 0, the rbfll bit has no meaning; it  should not be used as a status flag. the  tbemp bit in the sc2mod2 indicates whether transmit buffer 2 is empty when  double-buffering is enabled (sc2mod2.wbuf  =  1). it is set to 1 once a transmit frame  is transferred from transmit buffer 2 to transmit buffer 1 (shift register). the  tbemp bit is cleared to 0 when the tx19a core processor or dmac stores data in  transmit buffer 2. when wbuf = 0, the tb emp bit has no meaning; it should not be  used as a status flag.    12.3.17  transmit/receive buffer configuration    table 12.3.5   t ransmit/receive buffer configuration     wbuf  =  0  wbuf =  1  transmit single  double  uart  receive double  double  transmit single  double  i/o interface  (sclk  input)  receive double  double  transmit single  double  i/o interface  (sclk  output)  receive single  double      tmp19a71   12-16 

 tmp19a71          12.3.18  transmit/receive fifo buffers  as shown in  figure 12.3.5  and  figure 12.3.6 , a total of 16 bytes of fifo buffer is  ava ilable both in uart mode (excluding  9-bit uart mode) and  i/o interface mode.   when the fifo buffer is used for both tr ansmit and receive operations, 8 bytes are  assigned to each. when the fifo buffer is required for only transmit or receive, all  the 16 bytes can be used as transmit or receive buffers.     receive buffer 1 (shift register) receive buffer 2 (sc2buf) rx2 (p85) sc2fcnf. cnfg2 receive fifo internal bus   figure 12.3.5 receive fifo block diagram      transmit buffer 2 (sc2buf) transmit buffer 1 (shift register) tx2 (p86) sc2fcnf. cnfg2 transmit fifo internal bus   figure 12.3.6 transmit fifo block diagram      tmp19a71   12-17 

 tmp19a71            in sclk output mode (in i/o interface mode ), writin g data in the transmit buffer  starts a transmission in hal f-duplex mode. if the transmit buffer contains no data,  transmit operation is halted. setting the rx e bit in the sc2mod0 to 1 starts receive  operation in half-duplex mode. receive operation can be stopped by clearing the  sc2mod0.rxe bit to 0 before reading the  last frame. when the fifo buffer is  enabled, the following sequence must be executed to stop receive operation in  half-duplex mode.     1.   after receiving the last frame but one, disable the receive fifo.   2.  after receiving the last frame, disable receive operation by clearing the  sc 2mod0.rxe bit.   3.   enable the receive fifo with the same conditions as before.     (when the transmit fifo is enab led, it should be kept enabled.)  4.  read the data in the fifo.  5.   disable the receive fifo.  6.   read the last frame.     operation in full-duplex mode is the same as transmit operation in half-duplex mode.  the  received data must be  read before a next transmit frame has been written.     note 1:  when the transmit fifo is used, do not access registers other than the sc2buf, sc2frs, and  sc2fts.  note 2:  when the receive fifo is used, do not access the sc2cr or write to the sc2frs.  note 3:  do not write to the transmit fifo when it is full. before writing to the transmit fifo, check the  num ber of bytes stored in the transmit fifo by using the sc2fts.tlvl field.  note 4:  do not read from the receive fifo when it is empty. before reading the receive fifo, check the  num ber of bytes stored in the receive fifo by using the sc2frs.rlvl field.           tmp19a71   12-18 

 tmp19a71        12.3.19 signal generation timing  (1) i/o interface mode  table 12.3.6   si gnal generation timing in i/o interface mode  receive operation  sclk output mode immediately after the rising edge of the last sclk pulse  interrupt  (wbuf  =  0)  sclk input mode    immediately after the rising or falling edge of the last sclk pulse, as  programm ed  sclk  output mode   immediately after the rising edge of the last sclk pulse (i.e.,  immediately afte r the frame is tr ansferred to receive buffer 2) or  immediately after the frame is read from receive buffer 2  interrupt  (wbuf  =  1)  sclk input mode    immediately after the rising or falling edge of the last sclk pulse, as  programm ed (i.e., immediately afte r the frame is transferred to  receive buffer 2)  overrun error  sclk input mode  immediately after t he rising or falling edge of the last sclk pulse, a s  programmed  transmit operation  sclk  output mode immediately after the rising edge of the last sclk pulse  interrupt  (wbuf  =  0)  sclk  input mode    immediately after the rising or falling edge of the last sclk pulse, as  programm ed  sclk  output mode immediately after the rising edge of the last sclk pulse or  immediately  after the frame is transferred to transmit buffer 1  interrupt   (wbuf  =  1)  sclk  input mode    immediately after the rising or falling edge of the last sclk pulse, as  programm ed or immediately afte r the frame is transferred to  transmit buffer 1  underrun error   (wbuf=1)  sclk input mode  immediately after the rising or falling edge of the next sclk pulse, as  programm ed  note 1:  do not modify any control registers while data is being transmitted or received (receive  operation is enabled).   note 2:  do not disable receive operation (sc2mod0.rxe = 0) while data is being received.       tmp19a71   12-19 

 tmp19a71            (2) uart mode  table 12.3.7   si gnal generation timing in uart mode  receive operation  mode  9 data bits  8 data bits with parity  8 data bits with no parity,  7 data bits w ith parity  7 data bits wih no parity  interrupt  middle of the first stop bit middle of  the first stop bit middle  of the first stop bit  framing error  middle of the stop bit  middl e of the stop bit  middle of the stop bit  parity error   ?  middle of the last bit (i.e.,  parit y bit)  middle of the last bit (i.e., parity bit)  overrun error   middle of the stop bit  middl e of the stop bit  middle of the stop bit  transmit operation  mode  9 data bits  8 data bits with parity  8 data bits with no parity,  7 data bits w ith parity,  7 data bits with no parity  interrupt       (wbuf  =  0)   simultaneously with  transferring th e stop bit  simultaneously with  transferring th e stop bit  simultaneously with transferring the  stop bit  interrupt        (wbuf  =  1)   immediately after the  frame is transfer red to  transmit buffer 1 (i.e.,  simultaneously with  transferring the start bit) immediately after the  frame is transfer red to  transmit buffer 1 (i.e.,  simultaneously with  transferring the start bit)  immediately after the frame is  transferre d to transmit buffer 1 (i.e.,  simultaneously with transferring the  start bit)  note 1:   do not modify any control registers while data is being transmitted or received (or receive  operation is enabled).    note 2:  do not disable receive operation (sc2mod0.rxe = 0) while data is being received.  note 3:  the ?middle? in the above table means the 9th bit of sioclk.      tmp19a71   12-20 

 tmp19a71        12.4  register descripsion  (only c hannel 2 registers are described.)  table 12.4.1   sio register map  address  bits  mnemonic  register name  0xffff_c480  8  sc0mod0  serial 0 mode control register 0  0xffff_c481  8  sc0mod1  serial 0 mode control register 1  0xffff_c484  8  sc0cr  serial 0 control register  0xffff_c485  8  sc0mod2  serial 0 mode control register 2  0xffff_c488  8  br0cr  baud rate generator control register (sio0)  0xffff_c489  8  br0add  baud rate generator additional control register (sio0)  0xffff_c490  8  sc0buf  serial 0 tr ansmit/receive buf fer register  0xffff_c494  8  sc0fcnf  serial 0 fifo configuration register  0xffff_c498  8  sc0ftc  serial 0 fifo transmit control register  0xffff_c499  8  sc0frc  serial 0 fifo receive control register  0xffff_c49c  8  sc0fts  serial 0 fifo transmit status register  0xffff_c49d  8  sc0frs  serial 0 fifo receive status register  0xffff_c4a0  8  sc1mod0  serial 1 mode control register 0  0xffff_c4a1  8  sc1mod1  serial 1 mode control register 1  0xffff_c4a4  8  sc1cr  serial 1 control register   0xffff_c4a5  8  sc1mod2  serial 1 mode control register 2  0xffff_c4a8  8  br1cr  baud rate generator control register (sio1)  0xffff_c4a9  8  br1add  baud rate generato r additional control register (sio1)  0xffff_c4b0  8  sc1buf  serial 1 tr ansmit/receive buf fer register  0xffff_c4b4  8  sc1fcnf  serial 1 fifo configuration register  0xffff_c4b8  8  sc1ftc  serial 1 fifo transmit control register  0xffff_c4b9  8  sc1frc  serial 1 fifo receive control register   0xffff_c4bc  8  sc1fts  serial 1 fifo transmit status register  0xffff_c4bd  8  sc1frs  serial 1 fifo receive status register     note:  although these registers are 8-bit wide, two registers at consecutive addresses can be accessed simultaneously with a  16-bi t access instruction.      tmp19a71   12-21 

 tmp19a71            address  bits  mnemonic  register name  0xffff_c4c0  8  sc2mod0  serial 2 mode control register 0  0xffff_c4c1  8  sc2mod1  serial 2 mode control register 1  0xffff_c4c4  8  sc2cr  serial 2 control register   0xffff_c4c5  8  sc2mod2  serial 2 mode control register 2  0xffff_c4c8  8  br2cr  baud rate generator control register (sio2)  0xffff_c4c9  8  br2add  baud rate generator additional control register (sio2)  0xffff_c4d0  8  sc2buf  serial 2 tr ansmit/receive buf fer register  0xffff_c4d4  8  sc2fcnf  serial 2 fifo configuration register  0xffff_c4d8  8  sc2ftc  serial 2 fifo transmit control register  0xffff_c4d9  8  sc2frc  serial 2 fifo receive control register   0xffff_c4dc  8  sc2fts  serial 2 fifo transmit status register   0xffff_c4dd  8  sc2frs  serial 2 fifo receive status register   0xffff_c4e0  8  sc3mod0  serial 3 mode control register 0  0xffff_c4e1  8  sc3mod1  serial 3 mode control register 1  0xffff_c4e4  8  sc3cr  serial 3 control register  0xffff_c4e5  8  sc3mod2  serial 3 mode control register 2  0xffff_c4e8  8  br3cr  baud rate generator control register (sio3)  0xffff_c4e9  8  br3add  baud rate generato r additional control register (sio3)  0xffff_c4e0  8  sc3buf  serial 3 tr ansmit/receive buf fer register  0xffff_c4f4  8  sc3fcnf  serial 3 fifo configuration register  0xffff_c4f8  8  sc3ftc  serial 3 fifo transmit control register   0xffff_c4f9  8  sc3frc  serial 3 fifo receive control register   0xffff_c4fc  8  sc3fts  serial 3 fifo transmit status register   0xffff_c4fd  8  sc3frs  serial 3 fifo receive status register     note:  although these registers are 8-bit wide, two registers at consecutive addresses can be accessed simultaneously with a  16-bi t access instruction.        tmp19a71   12-22 

 tmp19a71          serial 2 mode control register 0    7  6 5  4 3 2  1 0  bit symbol  tb8  ctse  rxe  wu  sm  sc  read/write r/w  reset value  0  0 0  0 0 0  0 0  function  bit 8 of a  transmitted  character    handshake control  0: disable cts  operation  1:  enable cts  operation receive  control  0: disable 1: enable    wake-up  function  0: disable 1: enable serial transfer mode   00: i/o  interface mode  (for si o2, sio3 only)  01: 7-bit uart mode  10: 8-bit uart mode  11: 9-bit uart mode  serial clock (for uart) 00:  timer tb2out  01:  baud rate generator 10:  internal clock  (imclk)  11:  external clock  (sclk2  input)       (for sio2, sio3 only) sc2mod0  (0xffff_c4c0)              wake-up function    9-bit uart mode  other  modes  0 interrupt on every  received frame  1 interrupt only when  rb8 = 1  don?t care  0 disable (accept data streams  at all times)  1 enable  handshake ( cts ) control (for sio2, sio3 only)                        note 1:  in i/o interface mode, the serial control register (sc2cr) is used to select a serial clock.  note 2:  like the sio2, the sio0, sio1 and sio3 allows use of the timer tb2out as a serial clock.  note 3:  the sc2mod0, sc2mod1 and sc2mod2 registers must be set with the rxe bit cleared to 0. after  setti ng these registers, set the rxe bit to 1.  note 4:  during transmit operation in half-duplex mode (sc2mod1.fdpx=0) in i/o interface mode  (sc2m od0.sm=00), do not set the rxe bit to 1.  note 5:  the tb8 bit is not double-buffered. before writing to this bit, make sure that double-buffering is  disable d and no transmit operation is in progress.                 tmp19a71   12-23 

 tmp19a71          serial 2 mode control register 1    7  6 5  4 3  2 1  0  bit symbol  D fdpx  D uart D  D  D  D  read/write r/w  r/w  r/w  r/w  w  reset value 0  0 0  0 0  0 0  0  function    sync  method  0: half   duplex 1: full  duplex  uart  output  0: normal 1: 50%  dut y  cycle        sc2mod1  (0xffff_c4c1)    note:  when the n + (16 - k)/16 clock division function is used, the duty ratio varies with the value of k.           tmp19a71   12-24 

 tmp19a71        serial 2 mode control register 2    7 6 5  4 3 2 1 0  bit symbol  tbemp  rbfll  txrun sblen drchg wbuf  swrst  read/write r  r/w     reset value 1 0 0  0 0  0  00  function  transmit  buffer  empt y flag  0: full  1: empty  receive  buffer full  flag  0: empty  1: full  transmit-in -prog ress  flag  0: stopped 1: trans-  mitting  number of  stop bits  0: 1 bit  1: 2 bits  bit   sequence 0: lsb first 1: msb first double-  buffering  0: disable  1: enable  software reset  a write of 10 followed  b y a write of 01   sc2mod2  (0xffff_c4c5)    symbol  function  swrst  a write of 10 followed by a write of 01 to this fi eld r esets the module, thus initializing the rxe bit in  the sc2mod0, the tbemp, rbfll and txrun bits in the sc2mod2, the oerr, perr and  ferr bis in the sc2cr, and the internal circuits.   wbuf  enables or disables  double-buf fering for transmit (sclk output or input) or receive (sclk output)  operation in i/o interface mode and transmit oper ation in uart mode. for any other modes of  operation, double-buffering is always enabled.   drchg  specifies the bit transfer sequence in i/o inte rfa ce mode. in uart mode, the lsb is always  transferred first.   sblen  specifies the number of transmit stop bits in ua r t mode. for receive operation, a single stop bit is  used regardless of the setting of this bit.   txrun  a status flag indicating whether transmit shift operat ion is in progre ss. when this bit is set to 1,  transmit operation is in progress. when this bit is  cleared to 0, transmit operation is completed (if  tbemp = 1) or the trnamit buffer contains a next frame and is ready for transmission (if tbemp=  0).   rbfll  a flag indicating whether receive buffer 2 is fu ll.  the rbfll bit is set to 1 once a received frame  is transferred from receive buffer 1 to receive bu ffer 2.  it is cleared when the frame is read from  receive buffer 2. when double-buffering is disabled, the rbfll bit has no meaning.  tbemp  a flag indicating whether transmit buffer 2 is  empt y. the tbemp bit is set to 1 once a frame is  transferred from transmit buffer 2 to transmit buffer  1. it is cleared when a next frame is written to  transmit buffer 2. when double-buffering is  disabled, the tbemp bit has no meaning.     note 1:  if the module needs to be reset while it is transmitting data, two consecutive software reset  sequences (i.e., 10, 01, 10, 01) must be executed.  note 2:  this register does not support bit manipulation instructions.       tmp19a71   12-25 

 tmp19a71          serial 2 control register    7 6  5 4 3  2  1  0  bit symbol  rb8  even  pe  oerr  perr  ferr  sclks  ioc  read/write  r  r/w  r (cleared when read)  r/w  sc2cr  (0xffff_c4c4)  reset value  0 0  0 0 0 0 0  0    1: error has occurred.    function  bit 8 of a  received  character    parity type 0: odd  1: even  parity   0: enable  1: disable overrun  parity/  underru n framing  0: sclk2      1: sclk2  0: baud  rate  generato r 1: sclk2 input                                        input clock in i/o interface mode  (for ch2, ch3 only) framing error flag  parity error/underrun error  flag  overrun error flag  0 data is transmitted/received  on the sclk2 rising edge.                note 1:  all error flags are cleared to 0 when read.   note 2:  this register does not support bit manipulation instructions.   note 3:  the sc2cr.ferr bit should not be polled; instead, it should be read in the intrx2 interrupt routine  before  the receive buffer is read. for details, see the example in ? 12.5.3  8-bit uart mode ?.      1 data is transmitted/received  on the sclk2 falling edge.  active edge for sclk2 input  (for ch2, ch3 only) patiy type  0 baud rate generator  1 sclk2 pin input  0 odd parity  1 even parity    these bits are  cleared to 0  when read.      tmp19a71   12-26 

 tmp19a71        baud rate generator control register     7 6 5  4 3 2  1 0  bit symbol     dvs pre  br2s  read/write r/w  reset value  0  br2cr  (0xffff_c4c8)  0 0  0 0 0  0  0  function  must be  written as  0.  n  +   (16  ?  k)/16  division  function  0: disable 1: enable  00: imclk/2  01: imclk/8  10: imclk/32  11: imclk/128  clock divisor value n        clock source for baud rate generator  00 internal clock imclk/2  01 internal clock  imclk/8  10 internal clock  imclk/32  11 internal clock imclk/128    baud rate generator additional control register    7 6 5  4 3 2  1 0  bit  symbol        br2k  read/write        r/w  reset value  0 0 0  0 0 0  0  0  function           value k in n  +  16  ?  k)/16        clock divisor value for the baud rate generator   br2cr.dvs =  1   br2cr.dvs =  0  br2add  (0xffff_c4c9)          br2cr.             br2s  br2add.  br2k  0000 (n =  16) to  0001 (n =  1) 0010 (n =  2) to  1111 (n =  15) 0001 (n  =  1 ) (uart only) to  1111  n  =  15    0000  n  =  16    0000 prohibited  prohibited  divide  by   n  0001(k  =  1)  divide by n  to  1111(k =  15 )  prohibited  divide by  n  +   16 k)(16 ?   note 1:  the baud rate generator divisor cannot be set to 1 in uart mode if the n + (16 ? k)/16 clock division  function is enabled. in i/o interface mode, do not set the baud rate generator divisor to 1; setting the  divisor to 1 will cause incorrect operation.  note 2:  to use the n + (16 ? k)/16 clock division function, the value of k must be programmed in the  br2 add.br2k field before setting the br2cr.dvs bit to 1. however, the n + (16 ? k)/16 clock division  function is not usable when br2cr.br2s = 0000 (n = 16) or 0001 (n = 1).  note 3:  the n + (16 ? k)/16 clock division function can only be used in uart mode. in i/o interface mode, it must  be disa bled by clearing the br2cr.dvs bit to 0.      tmp19a71   12-27 

 tmp19a71            serial transmit/receive buffer register  7 6  5 4  3    2  1 0  bit symbol  tb  read/write w  reset value  0 0  0 0  0 0  0 0  function  transmit buffer      sc2buf  (0xffff_c4d0)  7 6  5 4  3 2  1 0  bit symbol  rb  read/write r  reset value  0 0  0 0  0 0  0 0  function  receive buffer  note:  in i/o interface mode (sc2mod0.sm = 0), do not write to the transmit buffer during receive operation  in half-duplex mode (sc2mod1.fdpx = 0).        tmp19a71   12-28 

 tmp19a71          serial 2 fifo configuration register    7  6 5  4 3  2 1  0  bit symbol  D  D  D  D  D  D  cnfg  read/write r  r/w  reset value 0 0  0 0  0  0  00  function         sc2fcnf  (0xffff_c4d4)      fifo    00: disable  01: transmit (16 bytes) 10: receive (16 bytes) 11: transmit/receive   (8 b ytes each)  note:  for continuous transmit/receive operations using the fifo, double-buffering must be enabled  (sc2mod2.wbuf=1).      serial 2 fifo receive control register    7 6  5  4 3  2  1 0  bit symbol  ril  rfis  rfcl  rfie  D  read/write r/w  w  r/w  r  reset value  0000  0  0  0  0  sc2frc  (0xffff_c4d9)  function  interrupt level  0000: interrupt is generated when the receive   fifo reaches 1 byte.  0001: interrupt is generated when the receive fifo reaches 2 bytes.   0010: interrupt is generated when the receive fif o reaches 3 bytes.  0011: interrupt is generated when the receive fif o reachs 4 bytes.   ?  1111: interrupt is generated when the receive  fif o reaches 16 bytes.   setting has no effect when cnfg=00/01.  the most significant bit must be cleared to 0  w hen cnfg=11.    interrupt  condition    0: interrupt  generated  only  when  ril=rlvl  1: interrupt  generated  w hen  ril Q rlvl fifo clear    sett ing this  bit to 1  clears  fifo  value.   (this bit is  always  read as 0.)  receive  fi fo  interrupt    0: disable  1: enable      rfis:  when rfis=0, a receive fifo interrupt is generated onl y when the number of bytes stored in the receive fifo  set in the sc2frs.rlvl matches the interrupt generation level set in the sc2frc.ril.   when rfis=1, a receive fifo interrupt is generated when the number of bytes stored in the receive fifo set  in the sc2frs.rlvl is equal to or greater than the interrupt generation level set in the sc2frc.ril.  note: this register does not support bit manipulation instructions.       tmp19a71   12-29 

 tmp19a71          serial 2 fifo transmit control register     7 6  5 4  3 2  1 0  bit symbol  til  tfis  tfcl  tfie  D  read/write r/w  w  r/w  r  reset value 0111  0  0  0  0  sc2ftc  (0xffff_c4d8)  function  interrupt level  0000: interrupt is generated when the transmit fifo reaches 1 byte.   0001: interrupt is generated when the transmit  fif o reaches 2 bytes.   0010: interrupt is generated when the transmit fifo reaches 3 byes.   0011: interrupt  is generated when the transmit fifo reaches 4 bytes.  ?  1111: interrupt is generated when the transmit fifo reaches 16 bytes.  setting has no effect when cnfg=00/10.  the most significant bit must be cleared to 0  w hen cnfg=11.  interrupt  condition    0: interrupt  generated  only  when  til=tlvl.  1: interrupt  generated  w hen  til R tlvl  fifo clear    setting this  bit to  1  clears the  fifo  value.  (this bit is  a lways  read as  0.)   transmit  fi fo  interrupt    0 di sable  1: enable    tfis:  when tfis=0, a transmit fifo interrupt is generated only when the number of bytes stored in the transmit  fifo set in the sc2fts.tlvl matches the interrupt generation level set in the sc2ftc.til.   when tfis=1, a transmit fifo interrupt is generated when  the number of bytes stored in the transmit fifo set  in the sc2fts.tlvl is equal to or smaller than the interrupt generation level set in the sc2ftc.til.   note: this register does not support bit manipulation instructions.   rlvl=00000 receive fifo: 0 bytes rlvl=00001 receive fifo: 1 byte  rlvl=10000 receive fifo: 16 bytes rlvl=00011 receive fifo: 3 bytes rlvl=00010 receive fifo: 2 bytes n5n5n5 data received data received data received data received data received fifo data read fifo data read fifo data read fifo data read fifo data read >! interrupt generated (rfis=1) >! interrupt generated (rfis=1) >! interrupt generated (rfis=1) interrupt  generated >" (rfis=0/1) tlvl=10000 transmit fifo: 16 bytes tlvl=01111 transmit fifo: 15 bytes tlvl=00000 receive fifo: 0 bytes tlvl=01101 receive fifo: 13 bytes tlvl=01110 transmit fifo: 14 bytes n5n5n5 data transmitted data transmitted data transmitted data transmitted data transmitted fifo data written  fifo data written fifo data written fifo data written fifo data written >! interrupt generated (tfis=1) >! interrupt generated (tfis=1) >! interrupt generated (tfis=1) interrupt  generated >" (tfis=0/1) when sc2frc.ril=0001 when sc2ftc.til=1110   figure 12.4.1   exam ple of interrupt generaton timing when using fifo   tmp19a71  12-30 

 tmp19a71        serial 2 fifo receive status register    7 6  5 4  3 2  1 0  bit symbol  rur  D  D rlvl  read/write r  reset value 0  0  0  00000  function  this bit is  set to 1  w hen the  receive  fifo is  full.   can be  read as 0.  can be  read as 0. receive fifo byte count  00000: 0 bytes  00001: 1 byte  00010: 2 bytes  00011: 3 bytes  ?  10000: 16 bytes  rur:  the rur bit is set to 1 if an attempt to store a new val ue is made when the receive fifo is already full. this bit  is cleared to 0 when it is read while the receive fifo buffer is not full.   note: this register does not support bit manipulation instructions.       serial 2 fifo transmit status register                           tur:  the tur bit is set to 1 when the transmit fifo beco mes empty. when the first byte is stored in the transmit  fofo, it is immediately transferr ed to the transfer buffer (sc2buf), c ausing the transmit fifo to become  empty and the tur bit to be set to 1. this bit is automat ically cleared to 0 when data is written to the transmit  fifo.         7 6  5 4  3 2  1 0  bit symbol  tur  D  D tlvl  read/write r  reset value 1  sc2frs  (0xffff_c4dd)  sc2fts  (0xffff_c4dc)  0  0  00000  function  this bit is  set to 1  w hen the  transmit  fifo is  empty.  can be  read as 0. can be  read as 0. transmit fifo byte count  00000: 0 bytes  00001: 1 byte  00010: 2 bytes  00011: 3 bytes  ?  10000: 16 bytes    tmp19a71   12-31 

 tmp19a71          12.5 operating modes  12.5.1  i/o interface mode  i/o interface mode utilizes a synchronizat ion clock (sclk), which can be configured  for either output mode in which the sclk clock is driven out from the tmp19a71 or  input mode in which the sclk clock is supplied externally.     (1) transmit operation (half-duplex)      sclk output mode   when transmit double-buffering is disabled (sc2mod2.wbuf = 0) in sclk  output m ode, each time the tx19a core processor writes a frame to the transmit  buffer, the 8 bits of the frame are shifted out on the txd2 pin, and the  synchronization clock is driven out from  the sclk2 pin. when all the bits have  been shifted out, the inttx2 interrupt is generated.   when transmit double-buffering is enabled (sc2mod2.wbuf = 1), a frame is  transf erred  from transmit buffer 2 to transmit buffer 1 (shift register) once the  tx19a core processor writes the frame to transmit buffer 2 when no data is being  transmitted or the last frame in transmit buffer 1 has been sent. at this time, the  transmit buffer empty flag (sc2mod2.tbemp) is set to 1 and the inttx2  interrupt is generated. if there is no data to be transferred from transmit buffer 2  to transmit buffer 1, however, the inttx2 interrupt is not generated and sclk2  output is stopped.       transmit data  write timing  sclk2 output  bit 0  bit 6 bit 7  bit 1  tx2  (inttx2)  bit 0      tbrun      figure 12.5.1   t ransmit operation in i/o interface mode   (sclk output mode, double-buffering disabled)      transmit data  write timing  sclk2 output  bit 0  bit 6 bit 7  bit 1  tx2  (inttx2)  bit 0  tbrun   tbemp    figure 12.5.2   t ransmit operation in i/o interface mode   (sclk output mode, double-buffer enabled, data in transmit buffer 2)    tmp19a71   12-32 

 tmp19a71          transmit data  write timing  sclk2 output  bit 0  bit 6 bit 7  bit 1  tx2  (inttx2)  tbrun   tbemp    figure 12.5.3   t ransmit operation in i/o interface mode  (sclk output mode, double-buffering enabled, no data in transmit buffer 2)          sclk input mode   when transmit double-buffering is disabled (sc2mod2.wbuf = 0) in sclk  input m ode, the 8 bits of a frame in the transmit buffer are shifted out on the tx2  pin when the sclk2 input becomes active (i .e., the first rising or falling edge, as  programmed) with transmit data written  in the transmit buffer. the tx19a core  processor must load a next frame into the transmit buffer by point a (shown in  figure 12.5.4 ).    when transmit double-buffering is enabled (sc2mod2.wbuf = 1), a frame is  transf erred from transmit buffer 2 to transmit buffer 1 (shift register) once the  tx19a core processor writes the frame to transmit buffer 2 before the sclk2  input becomes active or once the last frame in transmit buffer 1 has been sent.  at this time, the transmit buffer empt y flag (sc2mod2.tbemp) is set to 1 and  the inttx2 interrupt is generated. if the sclk2 input becomes active before a  frame is written to transmit buffer 2, an underrun error occurs and 8 bits of  dummy data (0xff) are sent although the  internal bit counter starts counting.        sclk2 input  (sclks = 0:  rising edge)  sclk2 input  (sclks = 1:  falling edge)  bit 0  bit 1  tx2  (inttx2)  bit 5 bit 6  bit 7 transmit data  write timing  bit 0  bit 1  a                          figure 12.5.4   t ransmit operation in i/o interface mode    (sclk input mode, double-bufferig disabled)              tmp19a71   12-33 

 tmp19a71            sclk2 input  (sclks = 0:  rising edge)  sclk2 input  (sclks = 1:  falling edge)  bit 0  bit 1  tx2  (inttx2)  bit 5 bit 6  bit 7 transmit data  write timing  bit 0  bit 1  a  tbrun  tbemp    figure 12.5.5   t ransmit operation in i/o interface mode  (sclk input mode, double-buffering enabled, data in transmit buffer 2)      sclk2 input  (sclks = 0:  rising edge)  sclk2 input:    (sclks = 1:  falling edge)  bit 0  bit 1  tx2  (inttx2)  bit 5 bit 6  bit 7 transmit data  write timing     1  a  tbrun  tbemp  perr (underrun error)    figure 12.5.6   t ransmit operation in i/o interface mode  (sclk input mode, double-buffering enabled, no data in transmit buffer 2)      tmp19a71   12-34 

 tmp19a71          (2) receive operation (half-duplex)      sclk output mode   when receive double-buffering is disabled (sc2mod2.wbuf = 0) in sclk  output m ode, each time the tx19a core processor picks up the frame in receive  buffer 1, the synchronization clock is driven out from the sclk2 pin to shift the  next frame into receive buffer 1. when a  whole-8-bit frame has been received in  receive buffer 1, the intrx2 interrupt is generated.   the sclk output is initiated by setting the sc2mod0.rxe bit to 1. when  rece ive double-buffering is enabled (sc2mod2.wbuf = 1), the frame received  first is transferred to receive buffer 2  and then a next frame is received into  receive buffer 1. once a frame is transferred from receive buffer 1 to receive  buffer 2, the receive buffer full flag (sc2mod2.rbfull) is set to 1 and the  intrx2 interrupt is generated.  after a frame has been transferred to receive buffer 2, the tx19a core  proc essor or dmac should read it before all 8 bits of a next frame are received.  otherwise, the intrx2 interrupt is not generated and sclk2 output is stopped.  if the tx19a core processor or dmac subsequently reads the frame in receive  buffer 2 in this state, the next frame is  transferred from receive buffer 1 to  receive buffer 2, generating the intrx2 interrupt to restart receive operation.          receive data  read timing  sclk2 output  bit 0  bit 6 bit 7 bit 1  rx2  (intrx2)  bit 0                          figure 12.5.7   re ceive operation in i/o interface mode  (sclk output mode, double-buffering disabled)      receive data  read timing  sclk2 output  bit 0  bit 6 bit 7 bit 1  rx2  (intrx2)  bit 0  bit7  rbfull                 figure 12.5.8   re ceive operation in i/o interface mode   (sclk output mode, double-buffering enabled, reading receive buffer 2)        tmp19a71   12-35 

 tmp19a71            receive data  read timing  sclk2 output  bit 0  bit 6 bit 7 bit 1  rx2  (intrx2)  bit7  rbfull    figure 12.5.9   re ceive operation in i/o interface mode   (sclk output mode, double-buffering enabled, not reading receive buffer 2)                sclk input mode   in sclk input mode, receive double-buffering is always enabled. a received  frame  is transferred to receive buffer 2 so that a next frame can be received  continuously into receive buffer 1.  the intrx2 interrupt is generated every time a frame is transferred from  rec eive buffer 1 to receive buffer 2.       sclk2 input  (sclks = 0:  rising edge)  sclk2 input  (sclks = 1:  falling edge)  bit 0  bit 1  rx2  (intrx2)  bit 5 bit 6  bit 7  receive data  read timing  bit 0  rbfull    figure 12.5.10   receive ope ration in i/o interface mode   (sclk input mode, reading receive buffer 2)      sclk2 input  (sclks = 0:  rising edge)  sclk2 input  (sclks = 1:  falling edge)  bit 0  bit 1  rx2  (intrx2)  bit 5 bit 6  bit 7  receive data  read timing  bit 0  rbfull  oerr                    figure 12.5.11     receive operation in i/o interface mode   (sclk input mode, not reading receive buffer 2)      tmp19a71   12-36 

 tmp19a71        note: to perform receive operation, the sc2mod0.rxe bit must be set to 1 in both sclk input and sclk output  modes.      (3) transmit/receive operation (full-duplex)  setting the sc2mod1.fdpx2 bit to 1  e nables full-duplex communication.     sclk output mode   when transmit/receive double-bufferig is disabled (sc2mod2.wbuf = 0) in  scl k output mode, each time the tx19a core processor writes a frame to the  transmit buffer, the synchronization clock is driven out from the sclk2 pin to  shift an 8-bit frame into receive buffer 1, generating the intrx2 interrupt. at  the same time, the frame written to the transmit buffer is shifted out on the tx2  pin. when all the bits have been shifted out, the transmit-done interrupt  (inttx2) is generated and sclk2 output is stopped. when the tx19a core  processor subsequently picks up the frame in the receive buffer and writes a next  frame to the transmit buffer, next transm it/receive operation starts, regardless of  whether the tx19a core processor first reads the receive buffer or writes data to  the transmit buffer.  when transmit/receive double-buffering is enabled (sc2mod2.wbuf = 1),  each tim e the tx19a core processor writes a frame to transmit buffer 2, the  synchronization clock is driven out from the sclk2 pin to shift an 8-bit frame  into receive buffer 1; it is then transferred to receive buffer 2, generating the  intrx2 interrupt. at the same time, the frame stored in transmit buffer 1 is  shifted out on the txd2 pin. when all the bits have been shifted out, the  transmit-done interrupt (inttx2) is generated and the next frame is transferred  from transmit buffer 2 to transmit buffer 1. durnig the above sequence, sclk  output is stopped if transmit buffer  2 becomes empty (sc2mod2.tbemp  =  1)  or if receive buffer 2 still contains data (sc2mod2.rbfull = 1). when the  tx19a core processor suqsequently picks up the frame in receive buffer 2 and  writes a next frame to transmit buffer 2,  sclk2 output is restarted so that next  transmit/receive operation starts.       receive data  read timing  sclk2 output  bit 0  bit 6 bit 7 bit 1  tx2  (inttx2)  bit 0  transmit data  w rite timing  (intrx2)  bit 5 bit 1 bit 0  bit 6 bit 7 bit 1  rx2  bit 0  bit 5 bit 1     figure 12.5.12   t ransmit/receive operation in i/o interface mode  (sclk output mode, double-buffering disabled)    tmp19a71   12-37 

 tmp19a71            receive data  read timing  sclk2 output  bit 0  bit 6 bit 7 bit 1  tx2  (inttx2)  bit 0  transmit data  w rite timing  (intrx2)  bit 5 bit 1 bit 0  bit 6 bit 7 bit 1  rx2  bit 0  bit 5 bit 1     figure 12.5.13   t ransmit/receive operation in i/o interface mode  (sclk output mode, double-buffering enabled, no next data)    receive data  read timing  sclk2 output  bit 0  bit 6 bit 7 bit 1  tx2  (inttx2)  transmit data  w rite timing  (intrx2)  bit 5 bit 0  bit 6 bit 7 bit 1  rx2  bit 5              figure 12.5.14   t ransmit/receive operation in i/o interface mode  (sclk output mode, double-buffering enabled, continuous transfer)    tmp19a71   12-38 

 tmp19a71          sclk input mode   when transmit double-buffering is disabled (sc2mod2. wbuf = 0) in sclk  input mode  (receive double-buffering is  always enabled in this mode), the tx19a  core processor must write a frame to the transmit buffer before the sclk2 input  becomes avtive. the 8 bits of a frame in th e transmit buffer are shifted out on the  tx2 pin, and the 8 bits of a received  frame are shifted into receive buffer 1,  synchronous to the programmed edge of th e sclk2 input. when all the bits have  been shifted out, the transmit-done inte rrupt (inttx2) is generated. when all  the bits have been received, the frame is transferred from receive buffer 1 to  receive buffer 2, generating the intrx2 interrupt. the tx19a core processor  must load a next frame into the transmit buffer before the sclk signal for the  next frame is input (i.e., by point a shown in figure 12.5.15 below). the tx19a  core processor must also pick up the fram e in receive buffer 2 before a next frame  has been received.   when transmit/receive double-buffering is enabled (sc2mod2.wbuf = 1), a  fram e is transferred from transmit buffer 2 to transmit buffer 1 once the last  frame in transmit buffer 1 has been sent. at this time, the inttx2 interrupt is  generated. when the 8-bit frame, received in parallel with transmission, has been  shifted into receive buffer 1, it is transferred to receive buffer 2, generating the  intrx2 interrupt. when the sclk2 is subsequently activated, the frame stored  in transmit buffer 1 is shifted out while a next frame is received into receive  buffer 1. if the tx19a core processor does not read the frame from receive buffer  2 before the last bit of a next frame is  received, an overrun error occurs. if the  tx19a core processor does not write a fr ame to transmit buffer 2 before the  sclk2 input is subsequently activated, an underrun error occurs.         a     receive data  read timing  sclk2 input  bit 0  bit 6 bit 7 bit 1  tx2  (inttx2)  bit 0  transmit data  w rite timing  (intrx2)  bit 5 bit 1 bit 0  bit 6 bit 7 bit 1  rx2  bit 0  bit 5 bit 1         figure 12.5.15   t ransmit/receive operation in i/o interface mode   (sclk input mode, double-buffering disabled)      tmp19a71   12-39 

 tmp19a71            receive data  read timing  sclk2 input  bit 0  bit 6 bit 7 bit 1  tx2  (inttx2)  bit 0  transmit data  w rite timing  (intrx2)  bit 5 bit 1 bit 0  bit 6 bit 7 bit 1  rx2  bit 0  bit 5 bit 1                         figure 12.5.16   t ransmit/receive operation in i/o interface mode  (sclk input mode, double-buffering enabled, no error occurred)      receive data  read timing  sclk2 input  bit 0  bit 6 bit 7 bit 1  tx2  (inttx2)  bit 0  transmit data  w rite timing  (intrx2)  bit 5 bit 1 bit 0  bit 6 bit 7 bit 1  rx2  bit 0  bit 5 bit 1 perr (underrun error)                            figure 12.5.17   t ransmit/receive operation in i/o interface mode  (sclk input mode, double-buffering enabled, an underrun error occurred)        tmp19a71   12-40 

 tmp19a71          12.5.2  7-bit uart mode  setting the sm field in the sc2mod0 to 01 puts the sio2 in 7-bit uart mode. in  this mode, the parity bit can be added to the transmitted frame, and the receiver can  perform a parity check on incoming data. parity can be enabled and disabled through  the programming of the pe bit in the sc2cr. when the pe bit is set to 1 to enable  parity, the sc2cr.even bit selects even or odd parity. the sblen bit in the  sc2mod2 specifies the number of stop bits.     example: transmitting 7-bit uart frames with an even-parity bit      start bit 0 1  2  3  5  4 6  even  parity  stop    clocking conditions:  system clock:  : 56 mhz    imbus clock   : 1/2 (28 mhz)    prescaler clock  : imclk/32    transfer rate  : 4800 bps (fsys = 56 mhz)        7 6  5 4 3  2 1 0     p8cr     ?   1  ?   ?   ?   ? ? ?   p8fr1     ?   1  ?   ?   ?   ? ? ?   configure the p86 pin as tx2.  sc2mod0    x 0  ?   x  0  1 0 1   select 7-bit uart mode.   sc2cr     x  1  1  x  x  x 0 0   select even parity.  br2cr     0  1  1  0  1  0 x 1   n=11, and k is valid.  imclk/32  br2add     0  0  0  0  1  0 1 0   set the transfer rate to 4800 bps. (k = 10)  imr52     ?   1 0  0  ?   1 0 0   enable the inttx2 interrupt and set its priority level to 4.  sc2buf     x  *  *  *  *  * * *   load the transmit buffer with a frame.  note: x = don?t care,   ? : no change          12.5.3  8-bit uart mode  setting the sm field in the sc2mod0 to 10 puts the sio2 in 8-bit uart mode. in  this mode, the parity bit can be added to the transmitted frame, and the receiver can  perform a parity check on incoming data. parity can be enabled and disabled through  the programming of the pe bit in the sc2cr. when the pe bit is set to 1 to enable  parity, the sc2cr.even bit selects even or odd parity.     example: transmitting 8-bit uart frames with an odd-parity bit     start bit 0 1 2 3  5  4 6  odd  parity  stop  7    clocking conditions  system clock  : 56 mhz    high-speed clock gear  : 1/2 (28 mhz)    prescaler clock  : imclk/32    transfer rate  :  9600 bps (fsys = 56 mhz)              tmp19a71   12-41 

 tmp19a71          ?   ?   settings in the main routine        7 6  5 4 3 2 1 0     p8ier     ?   ?   0  ? ? ? ? ?   p8fr1     ?   ?   1  ? ? ? ? ?   configure the p85 pin as rx2.  sc2mod0     ?   0  0  x 1 0 0 1   select 8-bit uart mode.   sc2cr     x  0  1  x x x x x   select odd parity.   br2cr     0  1  1  0 0 1 0 1   n=5, and k is valid.  br2add     0  0  0  0 0 1 0 1   set the transfer rate to 9600 bps. (k = 5)  imr53     ?   1 0  0 ? 1 0 0   enable the intrx2 interrupt and set its priority level to 4. sc2mod0     ?   ?   1 x ? ? ? ?   enable reception.    example of interrupt routine processing    iclr       0  1  1  0  1 0 1 0 0   clear the interrupt request.   reg.       sc2cr and 0x1c  if reg.     0 then error  reg.       sc2buf  read received data.  end of interrupt processing  note: x = don?t care,   ? : no change  check for errors.       tmp19a71  12-42 

 tmp19a71        12.5.4  9-bit uart mode  setting the sm field in the sc2mod0 to 11  puts the sio2 in 9-bit uart mode. in  this mode, the parity bit cannot be used and must be disabled by clearing the  sc2cr.pe bit to 0.   for transmit operation, the most-significant bit (9th bit) is stored in the tb8 bit in  the sc 2mod0. for receive operation, the most-significant bit is stored in the rb8 bit  in the sc2cr. reads and writes from and to the transmit and receive buffers must be  done with the most-significant bit first,  followed by the sc2buf. the sblen bit in  the sc2mod2 specifies the number of stop bits.    wake-up feature   in 9-bit uart mode, the wake-up feature can be enabled for slave controllers by  setting th e wu bit in the sc2mod0 to 1. wh en this feature is enabled, the intrx2  interrupt is generated only when sc2cr.rb8 = 1.         tx2  master  slave 1  slave 2  slave 3  rx2 tx2  rx2 tx2 tx2  rx2 rx2                     note:  the tx2 pin of a slave controller must be configured as an open-drain output by programming the port 8  open-drain control register (p8odcr).    figure 12.5.18   seri al link using the wake-up feature   tmp19a71   12-43 

 tmp19a71            protocol    (1)   put all the master and slave controllers in 9-bit uart mode.  (2)   ena ble the receiver in each slave controller by setting the sc2mod0.wu bit to 1.   (3)   t he master controller transmits an 8-bit address frame (i.e., select code) that identifies  a slave controller. the most-significant bit  (tb8) of an address frame is a 1.         slave controller select code  start bit 0  1  2  3  5  4 6  stop  7 8  ?1?     (4)   each sl ave controller compares the received address to its station address and clears  the wu bit to 0 if they match.   (5)   t he master controller transmits a block of data to the selected salve controller (with  sc2mod.wu = 0). the most-significant bit (tb8) of a data frame is a 0.     data  ?0? start bit 0  1  2  3  5  4 6  stop  7 bit 8     (6)  slave controllers not addressed (with sc2m od. wu = 1) continue to monitor the data  stream but discard any frames with the most -significant bit (rb8) cleared to 0. thus,  the receive-done interrupt (intrx2) is not generated. the addressed slave controller  (with sc2mod.wu = 0) can transmit data to th e mater controller to notify that is has  successfully receiv ed the message.     example:   connecting a master controller with two slave  controllers through a serial link using the imclk/2 clock  as a serial clock      tx2 master  slave 1  slave 2  select code  00000001  rx2 tx2 rx2 tx2 rx2  select code  00001010                          tmp19a71   12-44 

 tmp19a71        3)   master controller setings    main routine                   p8ier     ?   1 0  ? ? ? ? ?   p8cr     ?   1 0  ? ? ? ? ?   configure the p86 pin as tx2 and the p85 pin as rx2.   p8fr1     ?   1 1  ? ? ? ? ?    imr53     ?   1 0  0 ? 1 0 1   enable intrx2 and set its interrupt level to 5.   imr52     ?   1 0  0 ? 1 0 0   enable inttx2 and set its interrupt level to 4.   sc2mod0     1  0  1  0 1 1 1 0   select 9-bit uart mode and select imclk as a serial clock. sc2buf     0  0  0  0 0 0 0 1   load the select code for slave 1.                interrupt routine (inttx2)                   iclr       0  1  1  0  1 0 0 0 0   clear the interrupt request.  sc2mod0     0  ?   ?   ? ? ? ? ?   clear the tb8 bit to 0.  sc2buf     *  *  *  * * * * *   load transmit data.   end of interrupt processing        4)   slave controller settin gs    main routine                   p8ier     ?   1 0  ? ? ? ? ?    p8cr     ?   1 0  ? ? ? ? ?   set the p86 pin as tx2 (open-drain output) and the p85 pin as rx2. p8fr1     ?   1 1  ? ? ? ? ?    p8odcr     ?   1  ?   ? ? ? ? ?    imr53     ?   ?   1  1 0 1 1 0   enable inttx2 and intrx2.  imr52     ?   ?   1  10 101     sc2mod0     0  0  1  1 1 1 1 0   select 9-bit uart mode, select imclk as a serial clock and set the wu bit to 1.   interrupt routine (intrx2)               iclr       0  1  1  0  1 0 1 0 0   clear the interrupt request.   reg.          sc2cr and 0x1c  if reg.     0 then error  reg.          sc2buf  check for errors.  if  reg.  =  select code  then   sc2mod0     ?   ?   ?   0 ? ? ? ?   clear the wu bit to 0.         tmp19a71  12-45 

 tmp19a71        13.  analog-to-digital converters (adcs)  the tmp19a71 contains two 10-bit successive-approximation analog-to-digital converters  (adcs). both adcs have two modes; normal mo de and pmd mode. while normal mode supports  typical ad conversion with two 8-channel inputs, pmd mode is specifically designed for ad  conversion for motor control. in  pmd mode, the adcs have 8-channel and 11-channel inputs. the  two adcs can be programmed to operate independently, and the operating mode can be separately  selected for each of the adcs.     13.1 features  13.1.1 normal mode  1   two 8-channel, 10-bit ad conver ters are available. each chan nel has a separate conversion  result register.   2    the two ad converters can be independentl y programmed for fixed-channel or channel  scan mode.   3    the two ad converters can be independently programmed for single conversion or  continuous conversion mode.  4    the intad0/1 interrupt is generated upon completion of a conversion. the interrupt  interval is selectable.   5    setting register enables starting of an ad conversion under the following conditions:  ?   tmrb inte rrupt (inttb1)  ?   ext ernal trigger input (adtrg0/1)  ?   soft ware trigger (adsft0)  6    the highest-priority conversion can interrupt the ongoing conversion in channel scan and  fixed-channel continuous conversion modes (the highest-priority conversion can only  initiated by software).  7    the intadhp0/1 interrupt is generated upon completion of the highest-priority conversion.  8    ad conversions can be monitored vi a the busy and overrun flags.   9    in channel scan continuous conversion mode, the interval between conversions can be  selected.   10    the conversion result can be compared to the two compare registers. the user can select  whether or not to generate an interrupt when the conversion result equals the compare  register.     13.1.2 pmd mode  1   two 10-bit ad converters are available. one has 8 conversion result registers, and the other  has 11 conversion re sult registers.    2    the conversion enable, input channel and pmd timing trigger can be programmed  independently for each conversion result register.   3    conversions are started in ascending order from the smallest-numbered enabled conversion  result register.  4    the conversion interval can be increased by a maximum of 255 times the pmd trigger  interval.       tmp19a71   13-1  

 tmp19a71          13.2 register description  each of the two adcs contains a group of regi sters for both normal mode and pmd mode as  shown in  table 13.2.1 .    table 13.2.1 adc register map (1/3)  normal mode (adc0)  address  bits  mnemonic  register name  0xffffc900  16  adnres0  ad normal mode result register 0  0xffffc904  16  adnres1  ad normal mode result register 1  0xffffc908  16  adnres2  ad normal mode result register 2  0xffffc90c  16  adnres3  ad normal mode result register 3  0xffffc910  16  adnres4  ad normal mode result register 4  0xffffc914  16  adnres5  ad normal mode result register 5  0xffffc918  16  adnres6  ad normal mode result register 6  0xffffc91c  16  adnres7  ad normal mode result register 7  0xffffc920  16  adchpr0  highest-priority  conversion result register (adc 0)  0xffffc924  16(8)  adnmod0 (l)  ad normal mode control register  (low) (adc0)  0xffffc925  8  adnmod0h  ad normal mode control register high (adc0)  0xffffc928  8  adnclk0  ad normal mode clock control register (adc0)  0xffffc92c  16(8)  cmpctl0 (l)  ad monitor control register (low) (adc0)  0xffffc92c  8  cmpctl0h  ad monitor control register high (adc0)  0xffffc930  8  adchpc0  highest-priority  conversion cont rol register (adc0)  0xffffc934  16  adcmp00  ad compare register 0(adc0)  0xffffc938  16  adcmp01  ad compare register 1 (adc0)  0xffffc93c  16  adcbasn0  ad normal mode basic setting register (adc0)  0xffffc940  8  adcstart0  ad software start register (adc0)      tmp19a71   13-2  

 tmp19a71        table 13.2.2 adc register map (2/3)  normal mode (adc1)  address  bits  mnemonic  register name  0xffffc980  16  adnres8  ad normal mode result register 8  0xffffc984  16  adnres9  ad normal mode result register 9  0xffffc988  16  adnres10  ad normal mode result register 10  0xffffc98c  16  adnres11  ad normal mode result register 11  0xffffc990  16  adnres12  ad normal mode result register 12  0xffffc994  16  adnres13  ad normal mode result register 13  0xffffc998  16  adnres14  ad normal mode result register 14  0xffffc99c  16  adnres15  ad normal mode result register 15  0xffffc9a0  16  adchpr1  highest-priority  conversion result register (adc 1)  0xffffc9a4  16(8)  adnmod1 (l)  ad normal mode control register (low) (adc1)  0xffffc9a5  8  adnmod1h  ad normal mode control register high (adc1)  0xffffc9a8  8  adnclk1  ad normal mode clock control register (adc1)  0xffffc9ac  16(8)  cmpctl1 (l)  ad monitor control register (low) (adc1)  0xffffc9ac  8  cmpctl1h  ad monitor control register high (adc1)  0xffffc9b0  8  adchpc1  highest-priority  conversion cont rol register (adc1)  0xffffc9b4  16  adcmp10  ad compare register 0(adc1)  0xffffc9b8  16  adcmp11  ad compare register 1 (adc1)  0xffffc9bc  16  adcbasn1  a/d normal mode basic setting register (adc1)  0xffffc9c0  8  adcstart1  ad software start register (adc1)                pmd mode (adc0)  address  bits  mnemonic  register name  0xffffcd00  16  adpres0  ad pmd mode result register 0  0xffffcd04  16  adpres1  ad pmd mode result register 1  0xffffcd08  16  adpres2  ad pmd mode result register 2  0xffffcd0c  16  adpres3  ad pmd mode result register 3  0xffffcd10  16  adpres4  ad pmd mode result register 4  0xffffcd14  16  adpres5  ad pmd mode result register 5  0xffffcd18  16  adpres6  ad pmd mode result register 6  0xffffcd1c  16  adpres7  ad pmd mode result register 7  0xffffcd40  16(8)  adcsett00 (l)  ad input timing trigger register 0 (low) (adc0)  0xffffcd41  8  adcsett00h  ad input timing trigger register 0 high (adc0)  0xffffcd48  16(8)  adcset00 (l)  ad input port select register 0 (low) (adc0)  0xffffcd49  8  adcset00h  ad input port select register 0 high (adc0)  0xffffcd4c  16(8)  adcset01 (l)  ad input port select register 1 (low) (adc0)  0xffffcd4d  8  adcset01h  ad input port select register 1 high (adc0)  0cffffcd58  8  adpclk0  ad pmd mode clock control register (adc0)  0xffffcd5c  8  adpmod00  ad pmd mode control register 0 (adc0)  0xffffcd60  16(8)  adpmod01 (l)  ad pmd mode control register 1 (low) (adc0)  0xffffcd61  8  adpmod01h  ad pmd mode control register 1 high (adc0)  0xffffcd64  16(8)  adcne0 (l)  a/d count enable register (low) (adc0)  0xffffcd65  8  adcne0h  a/d count enable register high (adc0)  0xffffcd68  8  adcnt0  a/d conversion count setting register (adc0)  0xffffcd6c  16  adcbasp0  a/dpmd mode basic setting register (adc0)  0xffffcd70  8  admodsel0  ad mode control register (adc0)    tmp19a71   13-3  

 tmp19a71          table 13.2.3 adc register map(3/3)  pmd mode (adc1)  address  bits  mnemonic  register name  0xffffcd80  16  adpres8  ad pmd mode result register 8  0xffffcd84  16  adpres9  ad pmd mode result register 9  0xffffcd88  16  adpres10  ad pmd mode result register 10   0xffffcd8c  16  adpres11  ad pmd mode result register 11  0xffffcd90  16  adpres12  ad pmd mode result register 12  0xffffcd94  16  adpres13  ad pmd mode result register 13  0xffffcd98  16  adpres14  ad pmd mode result register 14  0xffffcd9c  16  adpres15  ad pmd mode result register 15   0xffffcda0  16  adpres16  ad pmd mode result register 16  0xffffcda4  16  adpres17  ad pmd mode result register 17  0xffffcda8  16  adpres18  ad pmd mode result register 18  0xffffcdc0  16(8)  adcsett10 (l)  ad input timing trigger register 0 (low) (adc1)  0xffffcdc1  8  adcsett10h  ad input timing trigger register 0 high (adc1)  0xffffcdc4  8  adcsett11  ad input timing trigger register 1  (adc1)  0xffffcdc8  16(8)  adcset10 (l)  ad input port select register 0 (low) (adc1)  0xffffcdc9  8  adcset10h  ad input port select register 0 high (adc1)  0xffffcdcc  16(8)  adcset11 (l)  ad input port select register 1 (low) (adc1)  0xffffcdcd  8  adcset11h  ad input port select register 1 high (adc1)  0xffffcdd0  16(8)  adcset12 (l)  ad input port select register 2 (low) (adc1)  0xffffcdd1  8  adcset12h  ad input port select register 2 high (adc1)  0xffffcdd8  8  adpclk1  ad pmd mode clock control register (adc1)  0xffffcddc  8  adpmod10  ad pmd mode control register 0 (adc1)  0xffffcde0  16(8)  adpmod11 (l)  ad pmd mode control register 1 (low) (adc1)  0xffffcde1  8  adpmod11h  ad pmd mode control register 1 high (adc1)  0xffffcde4  16(8)  adcne1 (l)  a/d counting  co nversion enable register (low) (adc1)  0xffffcde5  8  adcne1h  a/d counting co nversion enable register high (a dc1)  0xffffcde8  8  adcnt1  a/d conversion count setting register (adc1)  0xffffcdec  16  adcbasp1  a/dpmd mode basic setting register (adc1)  0xffffcdf0  8  admodsel1  ad mode control register  (adc1)  note 1: some of 16-bit adc registers is accessible in 8-bit system by dividing higher 8bits and lower 8 bits. i.e. adnmod0  becomes accessible in 8-bit system by making it be adnmod0l/adnmod0h.        tmp19a71   13-4  

 tmp19a71          the modsel bit in the admodsel0 register is used to select either normal mode  (modsel = 0) or pmd mode (modsel = 1). normal mode provides the ad monitor and  highest-priority conversion features. pmd mode is synchronous to the trigger inputs from a  programmable motor driver (pmd). in normal mode, the two adcs are basically functionally  equivalent; in the following description any  references to adc0 also apply to adc1.       ad mode control register (adc0)    7 6  5 4 3  2  1  0  bit symbol  D  D  D  D  D  D vrefon  modsel read/write r/w  reset value  0 0  0 0 0  0  0  0  function            vref  control  0: off  1: on  adc  conversion  mode    0: normal  mode   1: pmd  mode  a dmodsel0  (0xffff_cd70)    note 1: the mdosel bit must not be changed during an ad conversion. if it is changed, operation cannot be guaranteed.   note 2: registers other than those for the selected conversion mode must not be programmed. before programming registers,  the m odsel bit must be programmed to select normal or pmd mode.  note 3: the vrefon bit must be set 3 us before an ad conversion is started to ensure the stable internal reference voltage. if  an   ad conversion is started with vrefon= 0 or before the internal reference voltage has stabilized, conversion accuracy  cannot be guaranteed.   note 4: the vrefon bit is automatically set to 1 after an ad conversion is started. however, conversion accuracy cannot be  guara nteed until the reference voltage has stabilized (see note 3).           tmp19a71   13-5  

 tmp19a71            13.3  normal mode (admodsel0.modsel=0)    ad normal mode control register (low) (adc0)    7 6  3 4 3  2 1  0  bit symbol  D adch  lat  itm  rep  scan  read/write r/w  reset value  0 0  0 0 0  0 0  0  function  must be set  to 0.  analog input channel select  latency  0: none  1:  wait until  the  resul t  register  is read. interrupt in  fi xed-  channel  continuous  conv ersion  mode    continuous  conv ersion  mode  0: single  1: continu-       ous  channel  sca n mode 0:fixed-  channel 1: channel scan   a dnmod0(l)  (0xffff_c924)      analog input channel select  scan    adch0 [2:0]  0  fixed-channel mode 1  channel scan mode 000 ain0  ain0  001  ain1  ain0 to ain1  010  ain2  ain0 to ain2  011  ain3  ain0 to ain3  100  ain4  ain0 to ain4  101  ain5  ain0 to ain5  110  ain6  ain0 to ain6  111   ain7  ain0 to ain7  interrupt in fixed-channel continuous conversion  mode  fixed-channel continuous conversion mode scan = 0, rep = 1  0 generate an interrupt when a single  conversion has been completed.   1 generate an interrupt when a sequence of  four conversions has been completed.  ain7 ain15  ain5  ain13  ain6  ain14  ain4  ain12  ain2  ain10  ain3  ain11  ain1  ain9  ain0  ain8  in adc1, the input channels  correspond as fol lows:                      note 1: ain7 pin (ain15 pin for adc1) may be used as adtrg0 input pin. therefore, when adtrg0 is used in  adnmod0= ?10?, do not set to adnmod0=?111,?  and when adtrg1 is used in adnmod1=?11,?  do not set to adnmod1=?111.?  note 2: adnmod0 setting becomes effective only when it is in continuous conversion mode. when adnmod  0=?1? is set, the next conversion does not start until th e reading of the register stored at the end is finished.    for example, when adnmod0=?101,? adnmod0=?1,? adnmod0=?1,? and  a dnmod0=?1,? the next conversion does not start until reading of the result for adnres5 after channel scan  conversion has finished. when adnres5 is read prior to adnres0 ? 4, the next conversion starts as adnres5 starts to  be read. and, when adnmod0=?101,? adnmod0=?1,? adnmod0=?1,? adnmod0=?1,? and  adnmod0=?0,? the next conversion does not start unt il the results are stored four times in adnres5 and are  read out.      tmp19a71  13-6  

 tmp19a71          ad normal mode control register (high) (adc0)    15 14 13  12  11  10  9  8  bit symbol  D  D  D  D  D trge  tsel  read/write r  r/w  reset value  0 0 0  0  0  0  0  0  function       must be  set to 0.  must be  set to 0.  normal  mode  conversion  trigger   0: software  1: hardware  hardware trigger  source  00: reserved  01: inttbcom11  10: adtrg0  11: adtrg1  note 1: when =?1? is set, too, it can be started up by software.  note 2: adc1 also can select inttbcom11 as a hardware starting source by setting adnmod1=01.      ad software start register (adc0)    7  6 5 4  3 2 1  0  bit symbol  busy  eos  D  D  D  D  D adsft read/write r  r/w  r  w  reset value  0  0 0 0  0 0 0  0  function  normal  mode ad  conversion  busy flag   0: idle  1: busy  conversion  co mplete  flag  0: don?t   ca re  1:complet- ed    write a 0 to  cle ar this  bit.            a d   co nversion  start  0: don?t  car e  1:  st art    this bit is  alw ays  read as 0. note:  the busy bit indicates whether or not an ad conversion is in progress. use the eos bit to check whether or not an ad  conversion has completed.       a/d normal mode basic setting register (adc0)   7  6  5  4  3  2  1  0  bit symbol  D  D  D  D  D azsel  D  D  read/write r/w  reset value  0  0  0  0  0 0 0  0  function  must be  set to 0.  must be  set to 0.  must be  set to 0.  must be  set to 0.  must be  set to 0.   sample  hold time  1: 6 clocks  0: 12 clocks  must be  set to 0.   must be  set to 0.    15  14  13  12  11  10  9  8  bit symbol  D  D  D  D  D  D  D  D  read/write r/w  reset value  0 0  0  1  0 0  0  0  function  must be  set to 0.  must be  set to 0.   must be  set to 0.  must be  set to 1.  must be  set to 0.   must be  set to 0.   must be  set to 0.   must be  set to 0.   a dcstart0  (0xffff_c940)  (adnmod0h)  (0xffff_c925)  adcbasn0  (0xffff_c93c)  note: the time taken for the conversion of adc is derived from the equation, (the number of clocks selected in   27  clocks)/adclk.        tmp19a71   13-7  

 tmp19a71          highest-priority conversion  control register (adc0)    7 6 5  4 3 2  1  0  bit symbol  D  D  D  hbsy  hprq  hpch  read/write r  r/w  reset value  0 0 0  0 0 0  0  0  function      highest-  priority ad  co nversion  busy flag   0:  co mpleted 1: busy  highest-  priority  co nversion  request  0: don?t    car e  1: start  h ighest-  priority  conversion    highest-priority channel select    a dchpc0  (0xffff_c930)    highest-priority analog input channel select  scan    adch [2:0]  0  fixed-channel mode  000 ain0  001 ain1  010 ain2  011 ain3  100 ain4  101 ain5  110 ain6  111   ain7  ain7 ain15  ain6  ain14  ain5  ain13  ain4  ain12  ain3  ain11  ain2  ain10  ain1  ain9  ain0  ain8  in adc1, the input channels  correspond as fol lows:    note: ain7 pin (ain15 pin for adc1) may be used as adtrg0 input pin. therefore, when adtrg0 is used in  adnmod0= ?10,? do not set to adnmod0=?111,?  and when adtrg1 is used in adnmod1=?11,?  do not set to adnmod1=?111.?        tmp19a71   13-8  

 tmp19a71        there are 16 conversion result registers numbered from 0 to 15, which are all identical. the  following is a description of register 0.   ad normal mode conversion result register 0    7  6 5  4  3 2 1  0  bit symbol  adr  read/write r  reset value  0  0 0  0  0 0 0  0  function  lower 8 bits of an ad conversion result    15  14 13 12  11  10  9  8  bit symbol  val  ovr  D  D  D  D adr  read/write r  reset value  0  0 0 0 0 0 0  0  function  conversio n result  store flag  1: stored  overrun  flag  0: no  overrun 1: overrun         upper 2 bits of an ad  conversion result  a dnres0  (0xffff_c91c)  note 1: this register must be accessed as a 16-bit or larger  quantity. if it is accessed as an 8-bit quantity, operation cannot  be  guaranteed.   note 2: bit 15 is an ad conversion result flag adnres0. 1 is set to this when ad conversion value is stored, and it is  cleared t o 0 when the adnres0 is read.  note 3: bit 14 is an overrun flag adnres0. 1 is set to this when it is overwritten before reading the conversion result  register  adnres0. this bit is cleared to 0 when a new conversion result is stored in adnres0 with val=0.   note 4: this register does not support bit manipulation instructions.    highest-priority conversion result register (adc0)    7  6 5  4 3  2 1  0  bit symbol  adr  read/write r  reset  value  0  0 0  0 0  0 0  0  function  lower 8 bits of an ad conversion result    15  14  13  12  11 10  9  8  bit symbol  val  ovr  D  D  D  D adr  read/write r  reset value  0  0 0  0 0 0  0  0  function  conversion  r esult store  flag  1: stored  overrun  flag  0: no  overrun 1: overrun         upper 2 bits of an ad  conversion result  a dchpr0  (0xffff_c9020)  note 1: this register must be accessed as a 16-bit or larger  quantity. if it is accessed as an 8-bit quantity, operation cannot  be  guaranteed.   note 2: bit 15 is an ad conversion result flag adnres0. 1 is set to this when ad conversion value is stored, and it is  cleared t o 0 when the adnres0 is read.  note 3: bit 14 is an overrun flag adnres0. 1 is set to this when it is overwritten before reading the conversion result  register  adnres0. this bit is cleared to 0 when a new conversion result is stored in adnres0 with val=0.   note 4: this register does not support bit manipulation instructions.        tmp19a71   13-9  

 tmp19a71            ad normal mode clock control register 1    7 6  5 4 3  2 1  0  bit symbol  D  D  D  D  D adcck  read/write r  r/w  reset value  0 0  0 0 0  0 0  0  function         prescaler  clock  o utput  select  001: imclk/2  010: imclk/4  011: imclk/8  100: imclk/16  other: imclk  a dnclk0  (0xffff_c928)  note 1: ad conversion is performed at the clock frequency selected in this register. to assure conversion accuracy, however,  the conversion clock frequency must be 14 mhz or slower (which results in a conversion time of 2.36   s or longer with  6-clock sample hold).   note 2: the conversion clock must not be changed while ad conversion is in progress. wait at least 2 adclk clocks after ad  con version has completed before changing the conversion clock.         2  imclk  adcck  adclk0   4   8   16  ( ad conversion clock )                         figure 13.3.1   clo ck control circuit      tmp19a71  13-10  

 tmp19a71          a/d monitor control register (adc0)    7  6 5 4  3 2  1  0  bt symbol  D  D cmch0  cmop0  irqen0  cmcap0 read/write r  r/w  reset value  0  0 0 0  0 0  0  0  function     ad input channel 0 to be compared a/d monitor  interrupt  setting is 0.  0:under  compare register     1: more  than  compare  register  a/d monitor  inte rrupt  setting is 0.  0: disable  1: enable  a/d monitor  inte rrupt flag  is 0.  0:monitoring  non-gene-  rated  interru pt   1:monitoring  genera ted  interrupt   cmpctl0(l)  (0xffff_c92c)        cnch  ad input channel  t o be compared 000 ain0  001 ain1  010 ain2  011 ain3  100 ain4  101 ain5  110 ain6  111 ain7      ad monitor control register (adc0)    15  14 13 12  11  10  9  8  bit symbol  D  D cmch1  cmop1  irqen1  cmcap1 read/write r  r/w  reset value  0  0 0 0  0  0  0  0  function     ad input channel 1 to be compared a/d monitor  interrupt  setting is 1.  0:under  compare register     1: more  than  compare  register   a/d monitor  interrupt  setting is 1.  0: disable  1: enable  a/d monitor  interrupt flag  is 1.   0:monitoring  non-gene-  rated  interru pt  1:monitoring  genera ted  interrupt       cnch  ad input channel  t o be compared  000 ain0  001 ain1  010 ain2  011 ain3  100 ain4  101 ain5  110 ain6  111 ain7  ain7 ain15  in adc1, the input channels  correspond as follows:  ain0  ain8  ain1  ain9  ain7  ain15  ain6  ain14  ain5  ain13  ain4  ain12  ain3  ain11  ain2  ain10  ain6  ain14  ain5  ain13  ain4  ain12  ain3  ain11  ain2  ain10  ain1  ain9  ain0  ain8  in adc1, the input channels  correspond as fol lows:  (cmpctl0h)  (0xffff_c92d)    tmp19a71   13-11  

 tmp19a71            note: cmcapx is cleared to 0 by writing data in ?1? or in adcmpxx. because interrupt requests are continuously sent until this  register is cleared, it must be cleared within the monitor interrupt routine.       tmp19a71   13-12  

 tmp19a71        a/d conversion result compare register (adc0)    7 6 5  4 3 2  1  0  bit symbol  adr0  read/write r/w  reset value  0 0 0  0 0 0  0  0  function  a/d conversion result compare value 0 is stored.   15  14  13  12  11  10  9  8  bit symbol  D  D  D  D  D  D adr0  read/write r    reset value  0  0  0  0  0  0  0  0  function              a dcmp00  (0xffff_c934)      a/d conversion result compare register (adc0)    7 6 5  4 3 2  1  0  bit symbol  adr1  read/write r/w  reset value  0 0 0  0 0 0  0  0  function  a/d conversion result compare value 1 is stored.    15  14 13 12  11  10  9  8  bit symbol  D  D  D  D  D  D adr1  read/write r    reset value  0  0  0  0 0  0 0 0  function             a dcmp01  (0xffff_c938)      tmp19a71   13-13  

 tmp19a71          13.4.1  operation (normal mode)  13.4.1.1  analog reference voltage  clearing the vrefon bit in the admodsel0 turns off the switch between the vrefh  and frefl pins. once the vrefon bit is cleared, the internal reference voltage requires a  recovery time of 3   s to stabilize after the vrefon bit is  again set to 1. before starting an  ad conversion, therefore, be sure to wait for 3   s after setting the vrefon bit to 1. if an ad  conversion is started before this  stabilization period  has elapsed, conversion accuracy cannot  be guaranteed.     13.4.1.2  selecting an analog input channel(s)  selection of the analog input channel(s) to be used varies according to the operating mode  of the ad converter.              (1) normal ad conversion  when an analog input is used in channel fixed mode (adnmod0 = ?0?)  among the analog input from ain0 to ain 7, select one channel according to the  adn mod0 setting.  ?   ?   when an analog input is used in channel scan mode (adnmod0 = ?1?)  select one scan mode among the eight types scan modes according to the  adn mod0 setting.   (2) highest priority ad conversion    am ong the analog input from ain0 to ain 7, select one channel according to the  a/dchpc0 setting.     after resetting, adnmod0 is initialized to 0, and adnmod0to  0000, wh ich makes the selection be in proc essing, and channel fixed mode input of  ain0 pin is selected. note that pins not used  as analog input channels can be used as  normal ports (a part of them are for input  only), however, the conversion accuracy may  get worse.    when the highest-priority ad conversi on is started during the normal ad  conv ersion, the highest-priority one starts in a break, the normal ad conversion  resumes at the end of the highest-priority one is over.            example:  when the highest-priority conversion of ain7 is started in adchp0=111  durin g the continuous scan conversion of the channel from ain0 to ain3 in   adnmod0=11 and adnmod0=00011.  highest-priority ad  conversion startup  (software startup)  ch0     ch1     ch2    ch7      ch3      ch0     ch1 conversion ch    tmp19a71   13-14  

 tmp19a71          13.3.1.1  starting of ad conversion  ad conversion has two types; normal ad conversion and highest-priority ad conversion.  a normal ad conversion starts up in software by setting 1 to adcstart0. also,  the highest-priority conversion starts up in  software by setting 1 to adchpc0. a  for normal ad conversion, one operating mode among the four operating modes specified by  adnmod0. an operating mode of the highest-priority conversion is  channel-fixed single conversion only. a normal  ad conversion can start up with hardware  starting source sele cted by adnmod0 by setting 1 to adnmod0. when  this bit is ?10/11,? a normal ad conversion star ts up at the rising edge of adtrg0 pin, and  when ?01,? it starts up with inttbcom11 of the timer from 16-bit quantity. it can start in  software even if the startup in  hardware beco mes enabled.     when a normal ad conversion starts, 1 is set to an ad conversion busy flag  ( adcstart0) indicating that the conversion is in progress. when the  highest-priority ad conversion starts, 1  is set to an ad conversion busy flag  (adchpc0). at this time, a busy flag for normal ad conversion retains the value  before a starting of the highest-priority ad conversion. a conversion end flag  adcstart0 for normal ad conversion, also, retains the value before a starting of  the highest-priority ad conversion. since adcstart0 is a flag showing the  conversion operation, it has an interval of being 0 between the conversions such as those in  the continuous conversion mode. when palling the end of conversion, adcstart0  must not be used.    when 1 is set to adchpc0 during a normal ad conversion, the  high est-priority ad conversion starts upon th e storage of result register of the ongoing  conversion, and ad conversion (channel-fixed single conversion) of the cannel specified by  adchpc0 starts. when this result is stored in the result register adchpr0, a  normal ad conversion resumes operation from the part suspended.    13.3.1.2 restart  a normal ad conversion restarts when 1 is set to adcstart0 during the  channel-fixed normal conversion, or it is started with hardware source. at the time of  restarting, a normal ad conversion performed till then starts conversion after a lapse of  conversion time, however, the result that has been converted at the moment of restarting is  not stored. restarting does clear neither the flags of  nor .  note 1: when continuous conversion is in process, stop it first (adnmod0=0) and restart after all of the conversions  ended.   note 2: when channel scan mode conversion is in process, restart after all of the conversions ended.     13.3.1.3 stop repeat    changing the adnmod0 bit in  from 1 to 0 enables the stop of repeating after the  continuous conversion made  one-cycle repeat. in channel-fixed continuous conversion  mode (interrupts after four conversions), as  an interrupt generates after conversion is  performed four times, the continuous conver sion stops. in channel scan continuous  conversion mode, after the conversions performed as much as specified number of channels,  the continuous conversion stops as an interrupt is generated.      tmp19a71   13-15  

 tmp19a71            13.3.1.4  ad conversion mode and interrupt in the end of ad conversion  the normal mode has the four operating modes shown in table 13.3.1. normal ad  conversion can select a mode according to the adnmod0 setting while the  highest-priority ad conversion can select on ly channel-fixed single conversion regardless  of the adnmod0 setting.     table 13.3.1   rel ations of ad conversion mode, interrupt generation timing, and flag behavior        adnmod0  conversion mode  interrupt  gene ration timing eos  set timing  (note 1)  busy  (after an   interrupt has  generated )  itm rep  scan  fixed-channel  single conversion  after a conversion  ends  after a conversion  ends    0     0    0  channel scan  single conversion  after a scan  conversion ends  after a scan  conversion ends    0     0    1  every time of   conversion  after a conversion  ends.    1      0  fixed-channel  continuous conversion  every fur times of   conversion  after a conversion  ends four times    1      1    1        0    channel scan  continuous conversion  every time of  scan conversion  after a scan  conversion ends.    1          1    1  note 1: write 0 and clear eos.    (1) normal ad conversion  adnmod0 selects an operating mode. as an ad conversion starts, 1  is set t o adcstart0. after a specified ad conversion ends, 1 is set to  adcstart0 that indicates the ad conversion ended, and then an ad  conversion end interrupt (intad0) generates.   is cleared to 0 as  is set  when =?0.? there are timings to be 0 at the intervals of each channel  conversion when =?1.?    a)  fixed-channel single conversion mode  this mode is selected by programming the rep and scan bits in the adnmod0  reg ister to 00. in this mode, the adc performs a single conversion on a single selected  channel. when a conversion is completed,  the adc sets 1 to the adcstart0.eos bit,  clears the adcstart0.busy bit in 0 and generates the intad0 interrupt.  the eos  bit must be cleared by writing 0.   b)  channel scan single conversion mode  this mode is selected by programming the rep and scan bits in the adnmod0  reg ister to 01. in this mode, the adc performs a single conversion on each selected  group of channels. when a single conversion sequence is completed, the adc sets 1 to  the adcstart0.eos bit, clears the adcstart0.busy bit in 0 and generates the  intad0 interrupt. the eos bit must be cleared by writing 0.       tmp19a71   13-16  

 tmp19a71        c)  fixed-channel continuous conversion mode  this mode is selected by programming the rep and scan bits in the adnmod0  register to 10. in this mode, the adc repeatedly converts a single selected channel.  when a conversion process is completed, the adc sets 1 to the adcstart0.eos bit.  a generation timing of an interrupt re quest is selectable according to the  adnmod0 setting. the setting timing of  eos is associated with the timing of  an interrupt.  the eos bit must be cleared by writing 0.   when itm=0, the adc generates an interrupt request every time a conversion ends.  in this case,  the conversion result is stored in the corresponding conversion result  register to a selected channel, whic h makes 1 be set to the eos bit.    when itm=1, the adc generates an in t errupt after every four conversions  completed. the conversion result is stored  in the corresponding conversion result  register to a selected channel. after the result of the fourth conversion is stored, 1 is  set to the eos bit. and then, a conversion  starts again. the eos bit must be cleared  by writing 0.   adnmod0 setting can make the next conversion of the conversion in  contin uous conversion mode wait until the result register is read.   when itm=0, the time taken until a conver sion  starts after a previous conversion  ends is controlled, and when itm=1, the ti me taken until a conversion starts after  previous conversion ends four times is controlled.      d)  channel scan continuous conversion mode  this mode is selected by programming the rep and scan bits in the adnmod0  reg ister to 11. in this mode, the adc repeatedly converts the selected group of  channels. every time a scan conversion ends, 1 is set to adnmod0, and an  interrupt request of intad0 generates. adnmod0 has a timing that  becomes 0 at the interval of each channel  conversion. the eos bit must be cleared by  writing 0.     to stop the operation of conversion of continuous conversion modes, described in c)  and d ), 0 shall be written to adnmod0. the mode ends as an ongoing  conversion ends, and adnmod0 is cleared to 0.  stop ad conversions and set 0 to admodsel0 before transferring to a  stop m ode. the electricity is carried even it is in the stop mode unless the transfer is  made stopping a conversion. if the transfer is made with an ad conversion in  performing, the result come out after the releasing of the stop mode is not guaranteed.     (2) the highest-priority ad conversion  adnmod0 setting has no effect on the highest-priority ad  conv ersion. its operation mode is channel-fixed single conversion mode only. when  the starting condition is met, the highest-priority ad conversion of a specified  channel in adchpc0 is performed only one time. as the conversion ends, an  interrupt of the highest-priority ad conversion end generates, and  adchpc0 is cleared to 0.      tmp19a71   13-17  

 tmp19a71          13.3.1.5  highest-priority conversion mode  the highest-priority ad conversion can  interr upt a normal ad conversion. the  highest-priority ad conversion can start  by setting 1 to adchpc0. if the  highest-priority ad conversion starts during the normal ad conversion, ad conversion  result during the conversion process is stored  in a result register, and after that, a channel  specified by adchpc0is single-converted. that result is stored in adchpr0, and  the highest-priority ad conversion interrupt generates. then, the normal ad conversion  resumes from the part continued from the previous time. if the highest-priority ad  conversion restarts during the highest-priority ad conversion process, the conversion in  process is finished, and then the highest-priority conversion starts newly.    for example, if the continuous conversion of the channels from ain0 to ain7 is active,  and 1  is set to  while ain3 is converted, the channel specified by  is  converted as soon as the ain3 conversion ends , and the result is stored in adchpr0, and  then the continuous conversion restarts from ain4.    13.3.1.6 ad monitoring  each ad converter has two ad monitoring functions and can compare a conversion value  and tw o setting value simultaneously. when 1 is set to cmpctl0, an ad  monitoring is enabled. when the contents of a conversion result register specified by  cmpctl0 is more than or under the value of compare register (it is specified by  ), ad monitoring interrupt (intadm0) generates. cmpctl0 can  determine which setting condition is met. also,  this comparing operates every time a result  is stored in the relevant conversion result register, and as the condition is met, an interrupt  generates. note that since a regi ster assigned to ad  monitoring is not read in software in  general, the overrun flag adnres0 and the conversion result flag adnres0  are always set. therefore, to use the ad monitoring, do not use the flag of a relevant  conversion result register.    13.3.1.7 ad conversion time  one ad conversion takes 27 clocks excluding sampling clocks. in adcbasn0,6  or 12 c locks can be selected as sampling clocks, thus the sum of ad conversion clocks may be  33 or 39. adnclk0 selects an ad conversion clocks among the ad pre-scaler  output; imclk, imclk/2, imclk/ 4, imclk/8, and imclk/16.to assure the accuracy, it is  necessary to set the ad conversion clock less than 14mhz, i.e. under 2.36  s (if sample hold  is 6 clocks).    13.3.1.8  storage and read of  ad conversio n result   ad conversion results are stored  in th e result register of a normal ad conversion (from  adnres0 to adnres7). correspondence of result registers and analog input channels are  the same in any operating mode if they are in normal mode. for example, the result of ain0  conversion is always stored in the adnres0 register.  table 13.3.2  shows the correspondence of analog input channels and ad conversion result  registers.    tmp19a71   13-18  

 tmp19a71          table 13.3.2 analog input channel  and ad conversion register  analog input channel  conversion result register ain0 adnres0  ain1 adnres1  ain2 adnres2  ain3 adnres3  ain4 adnres4  ain5 adnres5  ain6 adnres6  ain7 adnres7      13.3.1.9 data polling  to process an ad conversion result by polling data without using any interrupt,  a dnmod0 is to be polled. when this flag is set, a conversion result is stored in a  predetermined ad conversion result register. therefore ad conversion result register must  be read after checking the set. to detect an  overrun at the time, the conversion result  register must be read in 16-bit system.  if the result were =0 and =1, a  conversion result not overwritten would be gained.    tmp19a71   13-19  

 tmp19a71            13.4.1  pmd mode (modsel=1)  in pmd mode, the adc performs ad conversions synchronous to a pmd trigger. the  pmd trigger can be selected from  three types: pmdtrg00 to pmdtrg02.    the adc0 has 8 conversion result registers while the adc1 has 11 conversion result  registers. for each  of these result registers,  an analog input port and a pmd trigger can be  programmed separately, and ad conversions ca n be enabled and disabled separately for  each register.  also, each of adc unit has a counter, and the two cycles; every time and the specified  num ber can be set to the counter. as all the programs enabled are converted completely, an  adc interrupt generates.      ad input timing trigger register (adc0)        7 6 5  4  3  2  1  0  bit symbol  adst3  adst2  adst1  adst0  read/write r/w  reset value  0 0 0  0  0  0  0  0  function  input timing trigger for  result register 3   00: pmdtrg00  01: pmdtrg01  10: pmdtrg02  11: reserved  input timing trigger for result register 2  00: pmdtrg00  01: pmdtrg01  10: pmdtrg02  11: reserved  input timing trigger for  result register 1  00: pmdtrg00  01: pmdtrg01  10: pmdtrg02  11: reserved  input timing trigger for result register 0  00: pmdtrg00  01: pmdtrg01  10: pmdtrg02  11: reserved   15  14  13  12  11  10  9  8  bit symbol  adst7  adst6  adst5  adst4  read/write r/w  reset value  0 0  0 0  0  0  0  0  function  a dcsettoo(l)  (0xffff_cd40)  (adcsettooh)  (0xffff_cd41)  input timing trigger for result register 4  00: pmdtrg00  01: pmdtrg01  10: pmdtrg02  input timing trigger for  result register 5  00: pmdtrg00  01: pmdtrg01  10: pmdtrg02  input timing trigger for  result register 7  00: pmdtrg00  01: pmdtrg01  10: pmdtrg02  11: reserved  input timing trigger for result register 6  00: pmdtrg00  01: pmdtrg01  10: pmdtrg02  11: reserved  11: reserved  11: reserved    tmp19a71   13-20  

 tmp19a71          ad input timing trigger register 0 (adc1)        7  6  5 4 3  2 1  0  bit symbol  adst11  adst10  adst9  adst8  read/write r/w  reset value  0  0  0 0 0  0 0  0  function    ad input timing trigger register 1(adc1)    7 6 5  4 3 2  1  0  bit symbol  D  D adst18  adst17  adst16  read/write r/w  reset value  0 0 0  0 0 0  0  0  function     input timing trigger for result register 10  00: pmdtrg10  01: pmdtrg11  10: pmdtrg12  11: reserved  input timing trigger for  result register 9  00: pmdtrg10  01: pmdtrg11  10: pmdtrg12  11: reserved  input timing trigger for result register 8  00: pmdtrg10  01: pmdtrg11  10: pmdtrg12  11: reserved  input timing trigger for  result register 11  00: pmdtrg10  01: pmdtrg11  10: pmdtrg12  11: reserved  input timing trigger for result register 10  00: pmdtrg10  01: pmdtrg11  10: pmdtrg12  11: reserved  input timing triffer for  result register 9  00: pmdtrg10  01: pmdtrg11  10: pmdtrg12  11: reserved  input timing triffer for  result register 8    00: pmdtrg10  01: pmdtrg11  10: pmdtrg12  11: reserved   15  14  13  12  11  10  9  8  bit symbol  adst15  adst14  adst13  adst12  read/write r/w  reset value  0 0  0  0  0 0  0  0  function  a dcsett1o(l)  (0xffff_cdc0)  (adcsett1oh)  (0xffff_cdc1)  input timing triggr for   result register 12   00: pmdtrg10  01: pmdtrg11  10: pmdtrg12  input timing trigger for result register 14  00: pmdtrg10  01: pmdtrg11  10: pmdtrg12  11: reserved  input timing trigger for  result register 13  input timing trigger for  result register 15   00: pmdtrg10  01: pmdtrg11  10: pmdtrg12  00: pmdtrg10  01: pmdtrg11  10: pmdtrg12  11: reserved  11: reserved  11: reserved  a dcsett11  (0xffff_cdc4)    tmp19a71   13-21  

 tmp19a71            ad input port select register 0 (adc0)        7  6  5 4 3  2  1  0  bit symbol  D adsi1  D adsi0  read/write r/w  reset value  0  0  0 0 0  0  0  0  function  must be  written as  0.     ad input port select register 1 (adc0)    input port for result register 1  000: ain0  001: ain1  010: ain2  011: ain3  100: ain4  101: ain5  110: ain6  111: ain7  must be  written as  0.   input port for result register 0  000: ain0  001: ain1  010: ain2  011: ain3  100: ain4  101: ain5  110: ain6  111: ain7   15  14  13  12  11  10  9  8  bit symbol  D adsi3  D adsi2  read/write r/w  reset value  0  0  0 0 0  0  0  0  function  must be  written as  0.   input port for result register 3  000: ain0  001: ain1  010: ain2  011: ain3  100: ain4  101: ain5  110: ain6  111: ain7  must be  written as 0.  input port for result register 2  000: ain0  001: ain1  010: ain2  011: ain3  100: ain4  101: ain5  110: ain6  111: ain7    7 6 5  4 3 2  1  0  bit symbol  D adsi5  D adsi4  read/write r/w  reset value  0 0 0  0 0 0  0  0  function  must be  written as  0.   input port for result register 5.  000: ain0  001: ain1  010: ain2  011: ain3  100: ain4  101: ain5  110: ain6  111: ain7  must be  written as  0.  input port for result register 4  000: ain0  001: ain1  010: ain2  011: ain3  100: ain4  101: ain5  110: ain6  111: ain7    15 14 13  12  11  10  9  8  bit symbol  D adsi7  D adsi6  read/write r/w  reset value  0 0 0  0 0 0  0  0  function  a dcset0o(l)  (0xffff_cd48)  (adcset0oh)  (0xffff_cd49)  a dcset01(l)  (0xffff_cd4c)  (adcset01h)  (0xffff_cd4d)  input port for result register 6  000: ain0  001: ain1  010: ain2  011: ain3  100: ain4  101: ain5  110: ain6  must be   written as input port for result register 7  000: ain0  001: ain1  010: ain2  011: ain3  100: ain4  101: ain5  110: ain6  must be   written as  0.   0.   111: ain7  111: ain7    tmp19a71   13-22  

 tmp19a71          ad input port select register 0(adc1)        7  6 5 4  3 2 1  0  bit symbol  adsi9  adsi8  read/write r/w  reset value  0  0 0 0  0 0 0  0  function  input port for result register 9  0000: ain8  0001: ain9  0010: ain10  0011: ain11  0100: ain12  0101: ain13  0110: ain14  0111: ain15  1000: ain16  1001: ain17  1010: ain18  other: reserved  input port for result register 8  0000: ain8  0001: ain9  0010: ain10  0011: ain11  0100: ain12  0101: ain13  0110: ain14  0111: ain15  1000: ain16  1001: ain17  1010: ain18  other: reserved    15 14  13 12  11  10  9  8  bit symbol  adsi11  adsi10  read/write r/w  reset value  0 0  0 0 0  0 0  0  function  a dcset1o(l)  (0xffff_cdc8)  (adcset1oh)  (0xffff_cdc9)  input port for result register 10  0000: ain8  0001: ain9  0010: ain10  0011: ain11  0100: ain12  0101: ain13  0110: ain14  0111: ain15  1000: ain16  1001: ain17  1010: ain18  input port for result register 11  0000: ain8  0001: ain9  0010: ain10  0011: ain11  0100: ain12  0101: ain13  0110: ain14  0111: ain15  1000: ain16  1001: ain17  1010: ain18  other: reserved  other: reserved    tmp19a71   13-23  

 tmp19a71          ad input port select register 1 (adc1)        7  6 5 4  3 2 1  0  bit symbol  adsi13  adsi12  read/write r/w  reset value  0  0 0 0  0 0 0  0  function  a dcset11(l)  (0xffff_cdcc)  input port for result register 12  0000: ain8  0001: ain9  0010: ain10  0011: ain11  0100: ain12  0101: ain13  0110: ain14  0111: ain15  1000: ain16  1001: ain17  1010: ain18  input port for result register 13  0000: ain8  0001: ain9  0010: ain10  0011: ain11  0100: ain12  0101: ain13  0110: ain14  0111: ain15  1000: ain16  1001: ain17  1010: ain18  other: reserved  other: reserved   15  14  13  12  11  10  9  8  bit symbol  adsi15  adsi14  read/write r/w  reset value  0  0  0 0 0  0 0  0  function  (adcset11h)  (0x ffff_cdcd)  input port for result register 14  0000: ain8  0001: ain9  0010: ain10  0011: ain11  0100: ain12  0101: ain13  0110: ain14  0111: ain15  1000: ain16  1001: ain17  1010: ain18  input port for result register 15  0000: ain8  0001: ain9  0010: ain10  0011: ain11  0100: ain12  0101: ain13  0110: ain14  0111: ain15  1000: ain16  1001: ain17  1010: ain18  other: reserved  other: reserved      tmp19a71   13-24  

 tmp19a71        ad input port select register 2 (adc1)        7  6 5 4  3 2 1  0  bit symbol  adsi17  adsi16  read/write r/w  reset value  0  0 0 0  0 0 0  0  function  a dcset12(l)  (0xffff_cdd0)  input port for result register 16  0000: ain8  0001: ain9  0010: ain10  0011: ain11  0100: ain12  0101: ain13  0110: ain14  0111: ain15  1000: ain16  1001: ain17  1010: ain18  input port for result register 17  0000: ain8  0001: ain9  0010: ain10  0011: ain11  0100: ain12  0101: ain13  0110: ain14  0111: ain15  1000: ain16  1001: ain17  1010: ain18  other: reserved  other: reserved   15  14  13  12  11  10  9  8  bit symbol  D  D  D  D adsi18  read/write r/w  reset value  0  0  0  0 0  0 0  0  function         input port for result register 18  (adcset12h)  (0x ffff_cdd1)  0000: ain8  0001: ain9  0010: ain10  0011: ain11  0100: ain12  0101: ain13  0110: ain14  0111: ain15  1000: ain16  1001: ain17  1010: ain18  other: reserved     tmp19a71   13-25  

 tmp19a71            ad pmd mode control register 0 (adc0)    7  6  5 4  3 2 1  0  bit symbol  adf0  D  D  D  D  D  D aden0 read/write  a dpmod00  (0xffff_cd5c)  r  r/w  reset value  0  0  0 0  0 0 0  0  function  conversion  complete flag       0: completed  1: in progress  or not  sta rted yet       ad  conversion 0: disable 1: enable   (adpmod10 used by adc1 also applies to these contents.)  note 1:  must be 1 as the starting condition, and it becomes 0 when all the conversions enabled are completed.  note 2: if 0 is set to =0 while the conversion is in progress, the value is set to the result register after the ongoing  chan nel conversion ends, and the operation stops. the next conversion starts not from the part where it stopped  but from a channel of the very beginning.    tmp19a71   13-26  

 tmp19a71        ad pmd mode control register 1 (used in adc0)        7 6  5  4 3  2 1  0  bit symbol  adpe7  adpe6  adpe5  adpe4 adpe3 adpe2  adpe1  adpe0   ad pmd mode control register 1 (used in adc1)      read/write r/w  reset value  0  0 0  0 0  0  0  0  function  result  register 7  enable  0: disable  1: enable  result  register 6  enable  0: disable 1: enable  result  register 5  enable  0: disable 1: enable result  register 4  enable  0: disable 1: enable result  register 3 enable  0: disable 1: enable result  register 2  enable  0: disable  1: enable  result  register 1  enable  0: disable  1: enable  result  register 0  enable  0: disable 1: enable  15  14  13  12  11  10  9  8  bit symbol  D  D  D  D  D  D  D  D  read/write r/w  reset value  0  0  0  0  0  0  0  0  function  must be  written as  0.   must be  written as  0.   must be  written as  0.   must be  written as  0.   must be  written as  0.   must be  written as  0.   must be  written as  0.   must be  written as  0.     7 6 5  4 3 2  a dpmod01(l)  (0xffff_cd60)  (adpmod01h)  (0xffff_cd61)  a dpmod11(l)  (0xffff_cde0)  (adpmod11h)  (0xffff_cde1)  1  0  bit symbol  adpe15  adpe14 adpe13 adpe12 adpe11 adpe10  adpe9  adpe8  read/write r/w  reset value  0 0 0  0 0 0  0  0  result  register 11 function  result  register 15   enable  0: disable  1: enable  result  register 14   enable  0: disable 1: enable  result  register 13 enable  0: disable 1: enable result  register 12 enable  0: disable 1: enable result  register 10   enable  0: disable  1: enable  result  register 9   enable  0: disable  1: enable  result  register 8   enable  enable  0: disable 0: disable 1: enable 1: enable   15 14 13  12  11  10  9  8  bit symbol  D  D  D  D  D adpe18  adpe17  adpe16 read/write r/w  reset value  0 0 0  0 0 0  0  0  result  register 18  enable  0: disable  1: enable  result  register 17   enable  0: disable  1: enable  result  register 16   enable  0: disable 1: enable must be  written as  0.   must be  written as  0.   must be  written as  0.   must be  written as  0.   function  must be  written as  0.     tmp19a71   13-27  

 tmp19a71            ad count enable register 0      ad count enable register 1    7  6  5  4  3 2 1  0  bit symbol    note 1: at least one channel must always be converted in the unit adc1. if all the channels are converted after    counting, the conversion is not skipped properly.      adcne7  adcne6  adcne 5 adcne4 adcne3 adcne2  adcne1  adcne0 read/write r/w  a dcne0(l)  (0xffff_cd64)  reset value  0 0  0  0  0 0  0 0  convert  the  conversion  register 3  after the  count  0:always  enable  1:enable  after the  count  convert  the  conversion  register 2  after the  count  0:always  enable  1:enable  after the  count  convert  the  conversion  register 1  after the  count  0:always  enable  1:enable  after the  count  convert  the  conversion  register 0  after the  count  convert  the  conversion  register 4  after the  count  0:always  enable  convert  the  conversion  register 5  after the  count  0:always  enable  convert  the  conversion  register 6  after the  count  0:always  enable  convert  the  conversion  register 7  after the  count  0:always  enable  function  0:always  enable  1:enable  after the  count  1:enable  after the  count  1:enable  after the  count  1:enable  after the  count  1:enable  after the  count   15  14  13  12  11  10  (adcne0h)  (0xffff_cd65)  9  8  bit symbol  D  D  D  D  D  D  D  D  read/write r/w  reset  value  0 0 0  0  0  0  0  0  function                  7 6  5 4 3 2  1  0  bit symbol  adcne15  adcne14 adcne13 adcne12 adcne11 adcne10 adcne9  adcne8 a dcne1(l)  (0xffff_cde4)  read/write r/w  reset value  0 0  0 0 0  0 0  0  convert  the  conversion  register 11  after the  count  0:always  enable  1:enable  after the   count  convert  the  conversion  register 10  after the  count  0:always  enable  1:enable  after the   count  convert  the  conversion  register 9  after the  count  0:always  enable  1:enable  after the   count  convert  the  conversion  register 8  after the  count  convert  the  conversion  register 12  after the  count  0:always  enable  convert  the  conversion  register 13  after the  count  0:always  enable  convert  the  conversion  register 14  after the  count  0:always  enable  convert  the  conversion  register 15  after the  count  0:always  enable  function  0:always  enable  1:enable  after the   count  1:enable  after the   count  1:enable  after the   count  1:enable  after the  count  1:enable  after t he  count    15 14  13 12  11  10  adcne1(h)  (0xffff_cde5)  9  8  bit symbol  D  D  D  D  D adcne18  adcne17  adcne16 read/write r/w  reset value  0 0  0 0 0  0 0  0  function          convert  the  conversion  register 18  after the  count  0:always  enable  1:enable  after the   count  convert  the  conversion  register 17  after the  count  0:always  enable  1:enable  after the   count  convert  the  conversion  register 16  after the  count  0:always  enable  1:enable  after t he  count    tmp19a71   13-28  

 tmp19a71          ad conversion count setting register 0 (used in adc0)    7 6 5  4 3 2  1  0  bit symbol  cmpcnt  a dcnt0  (0xffff_cd68)  read/write r/w  reset value  0 0 0  0 0 0  0  0  function  when the cycle val ue becomes the same value  as the value set here, a  channel set after countin g is also converted.  (adcnt1 used by adc1 applies to these contents.)    example of actual operation  setting  adpmod01=?1011_0111?   : conver sion ena bled(ch0,1,2,4,5,7)  adcne0  =?1111_0000?    : always convert  (ch0,1,2,3) o r after  counting (ch4,5,6,7)  adcnt0  =?0000_1111?    : count value(16 counts)  note 1: these are premised on that the  amount of pmdtrg capable of converti ng all the channels within a certain  cycle is available.    1)   a  channel changes from ch0 to ch1, and ch1 to ch2, then intad0 generates.  2)   t he count value decrements by one.  3)   go es to the step 1) if the count value is not 0, and to 4) if the value is 0 (after 16 cycles of conversion).  4)   a  channel changes from ch0 to ch1, ch1 to ch2, and so on till becomes ch7, then intad0  generates.  5)   l oads the register value  set as count set value.  6)   goes back t o the step 1).      ad pmd mode basic setting register (adc0)    7  6 5 4  3  2 1 0  bit symbol  D  D  D  D  D azsel  D  D  read/write r/w  reset value  0  0 0  0  0 0  0  0  function  must be  written as  0.   must be  written as  0.   must be  written as  0.   must be  written as  0.   must be  written as  0.   sample  hold time  a dcbasp0  (0xffff_cd6c)  1:6 clocks  0:12 clocks   must be  written as  0.   must be  written as  0.     15 14 13  12  11  10  9  8  bit symbol  D  D  D  D  D  D  D  D  read/write r/w  reset value  0  0  0  1  0  0  0  0  must be  written as  0.   function  must be  written as  0.   must be  written as  0.   must be  written as  1.   must be  written as  0.  must be  written as  0.   must be  written as  0.   must be  written as  0.   (adcbasp1 used by adc1 app lies to these contents.)  note 1: the conversion time of adc is derived from the equation; (the number of clocks selected in    27 clocks)/adclk.        tmp19a71   13-29  

 tmp19a71            ad pmd mode clock control register 0 (used by adc0)    7 6  5 4 3  2 1  0  bit symbol  D  D  D  D  D adpck  read/write r  r/w  reset value  0 0  0 0 0  0 0  0  a dpclk0  (0xffff_cd58)         prescaler  clock  o utput  select  function  000: imclk  001: imclk /2  010: imclk /4  011: imclk /8  100: imclk /16  101: fsys  other: reserved  (adpclk1 used by adc1 applies to these contents.)    note 1:  adc conversions are executed with clocks sel ected by above-mentioned registers. to guarantee  the accuracy, it is necessary to select a conversion  clock to make the conversion time less than 36   s (less than 14 mhz in an ad clock).  note 2: a conversion clock must not be changed du rin g an ad conversion in progress. more than two  clocks of adclk after the conversion stops, it must be changed.                                figure 13.3.2 clock control circuit     2  imclk  adpck0  adclk   4   8   16  fs y s  (clock for ad conversion)      tmp19a71  13-30  

 tmp19a71        there are the same registers from 0 to 18 as the result registers.  here the register 0 is described.    ad pmd mode result register 0    7  6 5 4  3  2  1  0  bit symbol  adr07  adr06 adr05 adr04  adr03  adr02  adr01  adr00 read/write r  a dpres0  (0xffff_cd00)  reset value  0  0 0 0  0  0  0  0  function  lower 8 bits of an ad conversion result    15  14 13 12  11  10  9  8  bit symbol  val  ovr  D  D  D  D adr09  adr08  read/write r  reset value  0  0 0 0 0 0  0  0  overrun  flag  result  store flag  function  0: no  overrun 1: overrun     1: stored      upper 2 bits of an ad  conversion result    note 1: to access this register, the system of more than 16-bit is to be used. when accessed by 8-bit system,  the operation shall not be guaranteed.  note 2: bit 15 is an ad conversion result flag .  w hen an ad conversion value is stored, 1 is set to it.  when this register (adpres) is  read, it is cleared to 0.  note 3: bit 14 is an overrun flag. 1 is set to th is flag  when a conversion result is overwritten before  reading the conversion result register (adpres) . it is cleared to 0 with a flag reading.  note 4: this register is not accessible with any bit operation instruction.      tmp19a71   13-31  

 tmp19a71          13.4.2 operation (pmd mode)   13.4.2.1  analog reference voltage  by writing 0 to the admodsel0 bit, a switch between vrefh and vrefl  can be turned off. to start an ad conversion, 1 must be written to the  bit, and  then it must be waited for more than 3   s until an internal reference voltage is stabilized.  the conversion accuracy when the conversion is started waiting for less than 3  s shall not  be guaranteed.    13.4.2.2 basic operation  in pmd mode, a conversion result register becomes the reference of ad conversions. each  conversion result register sets conversion enabled (adpmod01), conversion trigger  (adcsett00), and input ports (adcset0x).  setting 1 to adpmod00 causes the  wait state of a conversion trigger.  as a conversion trigger from pmd is accepted, ad conversion is executed in ascending  ord er from the conversion result register of the smallest number set in the conversion  enabled.  an accepted conversion trigger is retained inside until the conversions of a whole unit are  com pleted. when a conversion result register to be executed next is set to the trigger already  accepted, a conversion starts immediately.     13.4.2.3  ad conversion counting  in pmd mode, there is an ad conversion count function that enables a skip a conversion  trigger (pmdtrg) of a specific  result register  for the set number of times. by using this  function, both a result register whose conversion is desired in every cycle and a result  register whose conversion cycle may delay can be controlled in the same unit. the skip,  however, is not possible for all the result registers whose conversions are enabled in the unit.   figure 13.3.3  shows an ad conversion operation in pmd mode.      tmp19a71   13-32  

 tmp19a71        set 1 to adpmod00.  adcnt=?0?    a skip of this conversion  register is invalid?  (adcnex=0?)  set a certain value to adcnt0  no  no  yes  any setting input trigger   ad conversion starts  the last conversion  register?  ? an interrupt generation  ? conversion register number=0  ? circuit retaining trigger is cleared  ? adcnt0 is changed to -1   yes  yes  yes  no  no      figure 13.3.3 pmd mode operation     tmp19a71   13-33  

 tmp19a71            13.4.2.4 ad conversion time  the number of clocks of ad conversion for one cycle is 27 excluding sampling clocks. since  the adcbasp0 bit can select a sampling clock from 6 or 12 clocks, the sum of ad  conversion clocks becomes 33 or 39. adpclk0 selects an ad conversion clock  among an ad prescaler output fsys, imclk,  imclk/2, imclk/4, im clk/8, and imclk/16.  to ensure its accuracy, ad conversion clock must  be set less than14mhz, i.e. more than 2.36   s of ad conversion time (when sample hold is 6 clocks).    13.4.2.5 data polling  to process an ad conversion result by  polling data without using any interrupt,  adpmod00 should be polled. when this flag is cleared to 0, a conversion result is  stored in a prescribed ad conversion result register. therefore the result resister must be  read after checking the set. to detect any ove rrun at this time, a conversion result register  must be read in 16-bit system. if the  result came out as =0 and =1, a  conversion result that was not overwritten would be gained.           tmp19a71   13-34  

 tmp19a71          13.5 operating timing  in pmd trigger mode, setting adpmod00 enables the acceptance of a pmd trigger,  and inputting pmdtrg00/01 starts a converting operation. after all the program conversions  end, adf is cleared as an interrupt request is output, and then the next input of pmdtrg00/01  is waited. when aden is cleared, adf is cleared without waiting for the end of all the program  conversions.  inputting of the same pmd trigger whose conversion  is in proc ess is ignored, while a different  input is retained. a program conversion of a di fferent pmd trigger is processed continuously  immediately after the one of the previous trigger.      aden    adf    intad  pmdtrg00    pmdtrg01  1     2  3  1  1     2  3    figure 13.5.1   t iming chart 1 in pmd mode      1     2     3  aden    adf    intad  pmdtrg00    pmdtrg01  1  1     2     3    figure 13.5.2     timing chart 2 in pmd mode        tmp19a71   13-35  

 tmp19a71          13.6  example of use  13.6.1  pwm peak synchronization (read once)    example of use: connect a u-phase current ct output to ain0, and v-phase current ct output to ain1.  a  conversion is processed at the pwm carri er peaks (pwm counter=mdprd). a result  of ain0 is stored in adpres0, and a result of ain1 to adpres1.        pwm counter=max(mdprd) pwm counter=1 triangular wave      pwm u-phase       v-phase       w-phase    conversion timing  adf  result processing    figure 13.6.1   a d converter    example of use 1  timing      setting    ? admodsel0 = **** **** **** ***1: pmd mode  ? adpmod00 = **** **** **** ***1  : adc enabled  ? adpmod01 = 0000 0000 0000 0011:select result register 1 or 2  ? adcset00= **** **** 0001 0000  : select ain  ? adcsett00= **** **** **** 0000 : select pmdtrg0  ? t rgcr0 = **** **** **** *100  : pmd trigger setting    operation  ? at the first pwm carrier peak after 1 is set  to  aden, a conversion starts. adf becomes 1.  it, however, does not start when a triangul ar wave (pwm counter) is in idle state.  ? a conversion is processed in ascending order from the smallest  program number (conversion  register num ber).  program 0 converts with ain0 as an input and put the result in adpres0.  program 1 converts with ain1 as an input and put the result in adpres1.  ? as adf becomes 0,  an interrupt intad0 generates.    result processing    read adpres0 and adpres1 after checking if adf is 0 or in the interrupt processing of  fin ishing all ad conversions, use them  as a u-phase and v-phase currents.    tmp19a71   13-36  

 tmp19a71        13.6.2  pwm peak synchronization (read once)  example of use: connect u-phase current to ain1, v- phase current to ain2, and w-phase current to in3.  the conversion is supposed to be performed  at the peak of a triangular wave (pwm  counter=max). the result of ain1 is store  in adpres0 and 3, the result of ain2 in  adpres1 and 4, and the result of ain3 in adpres2 and 5.        pwm counter=max(mdprd)  pwm counter=1  triangular wave    pwm  u-phase        v-phase        w-phase    setting timing  conversion timing adf  result processing  ii)setting  i)setting    figure 13.6.2   a d converter    example of use 2   timing    i) setting   ? admodsel0 = **** **** **** ***1: pmd mode  ? adpmod00 = **** **** **** ***1  : adc enabled  ? adpmod01 = 0000 0000 0011 1111: select result register 0,1,2,3,4,or 5  ? adcset00= 0001 0011 0010 0001 : select ain   ? adcset01= **** **** 0011 0010  : select ain    ? adcsett00= **** 0000 0000 0000: select pmdtrg0  ? t rgcr0 = **** **** **** *100  : pmd trigger setting    i) operation   ? a conversion starts at the first peak of triangular wave after 1 is set  to aden. adf becomes 1.  ? pr ogram 0 converts with ain1 as an input and put the result in adpres0.  ? pr ogram 1 converts with ain2 as an input and put the result in adpres1.  ? pr ogram 2 converts with ain3 as an input and put the result in adpres2.  ? pr ogram 3 converts with ain1 as an input and put the result in adpres3.  ? pr ogram 4 converts with ain2 as an input and put the result in adpres4.  ? pr ogram 5 converts with ain3 as an input and put the result in adpres5.  ? s ince the settings of adpe7 and 6 are off,  all programs end. adf becomes 0.    tmp19a71   13-37  

 tmp19a71            13.6.3  synchronization to an optional timing of pwm cycle (read twice)  example of use: connect th e dc-shunt output to ain1. a single  shunt system executes conversions at  the timing where all u, v, w are other than h or l. output data is to be updated every  pwm cycle, and a current is to be detected every pwm cycle.      pwm counter=1 pwm counter=max(mdprd) triangular wave    pwm u-phase       v-phase       w-phase    setting timing  conversion timing adf result processing   u v w w u v v w u   figure 13.6.3   a d converter   example of use 3   timing    i) setting  ? admodsel0 = **** **** **** ***1: pmd mode  ? adpmod00 = **** **** **** ***1: adc enabled   ? adpmod01 = 0000 0000 0000 1111: select a conversion register0, 1, 2, or 3   ? adcset00= 0001 0001 0001 0001 : select ain   ? adcsett00= **** **** 0101 0000 : select pmdtrg0 or 1  ? t rgcr0 = **** **** **00 1001  : pmd trigger setting  ? t rgcmp00 = any of cmpu-cmpv:  pmd trigger timing setting  ? tr gcmp01 = any of cmpv-cmpw:  pmd trigger timing setting    i) operation  ? t rg0md and trg1md are 001 after 1 is set to aden, and trgcmp00 and 01 have effect  at  the max of a pwm counter.  ? a conversion starts when pwm counter= trgc mp00. adf bec omes 1. program 0 and 1 with  pmdtrg0 selected convert with ain1 as an input and put the results in adpres0 and 1  each.  ? a  conversion starts when pwm counter=t rgcmp01. program 2 and 3 with pmdtrg1  selected convert with ain1 as an input and put the results in adpres2 and 3 each.  ? s ince the settings of ad7-4 are off, the program ends here. adf becomes 0.    i) result processing   iu=(adpres0+adpres1)/2   iw=(adpres2+adpres3)/2    ii) setting  ? admodsel0 = **** **** **** ***1: pmd mode  ? adpmod00 = **** **** **** ***1: adc enabled  ? adpmod01 = 0000 0000 0000 1111:program 0, 1, 2, and 3 enabled  ? adcset00= 0001 0001 0001 0001 : select ain  ? adcsett00= **** **** 0101 0000 : select pmdtrg0 or 1    tmp19a71   13-38  

 tmp19a71        ? trgcr0 = **** **** **00 1001  : pmd trigger setting    ? trgcmp00 = any of cmpw ? cmpu : pmd trigger timing setting  ? tr gcmp01 = any of cmpu ? cmpv : pmd trigger timing setting    ii) operation  ? since trg 0md/trg1md=001 trgcmp00 and 01 have  effect where pwm counter is the max.  ? a conversion starts when pwm counter=trgcmp00. adf becomes 1. program 0 and 1 with  pmdtr g0 selected converts with ain1 as an input and put the result in adpres0 and 1  each.  ?   a conversion starts when pwm counter=trgcmp01. program 2 and 3 with pmdtrg1  selected convert with ain1 as an input and put the results in adpres2 and 3 each.  ? s ince the settings of ad7-4 are off, the program ends here. adf becomes 0.    ii) result processing     iw=(adpres0+adpres1)/2 iv=(adpres2+adpres3)/2      tmp19a71   13-39  

 tmp19a71        14.  motor control circuit (p md: programmable motor driver)  the tmp19a71 contains a two-channel programmabl e motor driver (pmd). in addition to a  3-phase waveform generation circu it, the pmd also has a sync samp ling signal generation circuit  for sampling operations of the ad converter. by implementing these functions by hardware, the  load on software can be reduced, and vector  control of brushless dc  motors can easily be  implemented.     14.1  functional block diagram  ain  ad converter  trg    pmd    3-phase waveform  gene ration circuit  port  u to z  port  emg  emg  sync sampling  signal generation  circuit tx19a  core  processor   im bus                                            figure 14.1.1   pm d functional block diagram        tmp19a71   14-1  

 tmp19a71          14.2 pmd registers  table 14.2.1   pmd register map   address  bits  mnemonic  register  name   0xffff_c300  16  mdcr0  pmd0 control register  0xffff_c304  16  mdcnt0  pmd0 count register  0xffff_c308  16  mdprd0  pmd0 period register  0xffff_c30c  16  cmpu0  pmd0 compare register u  0xffff_c310  16  cmpv0  pmd0 compare register v  0xffff_c314  16  cmpw0  pmd0 compare register     0xffff_c318  16  mdout0  pmd0 output register  0xffff_c31c  16  emgrel0  emg0  release  register  0xffff_c320  16  emgcr0  emg0 control register  0xffff_c324  16  trgcr0  trigger control register (pmd0)  0xffff_c328  16  trgcmp00  trigger compare 0 register (pmd0)  0xffff_c32c  16  trgcmp01  trigger compare 1 register (pmd0)  0xffff_c330  16  trgcmp02  trigger compare 2 register (pmd0)  0xffff_c340  16  mdcr1  pmd1 control register  0xffff_c344  16  mdcnt1  pmd1 count register  0xffff_c348  16  mdprd1  pmd1 period register  0xffff_c34c  16  cmpu1  pmd1 compare register u  0xffff_c350  16  cmpv1  pmd1 compare register v  0xffff_c354  16  cmpw1  pmd1 compare register w  0xffff_c358  16  mdout1  pmd1 output register  0xffff_c35c  16  emgrel1  emg1  release  register  0xffff_c360  16  emgcr1  emg1 control register  0xffff_c364  16  trgcr1  trigger control register (pmd1)  0xffff_c368  16  trgcmp10  trigger compare 0 register (pmd1)  0xffff_c36c  16  trgcmp11  trigger compare 1 register (pmd1)  0xffff_c370  16  trgcmp12  trigger compare 2 register (pmd1)      note:  these registers must be accessed as a 16-bit quantity, unless otherwise noted. these registers do not support bit  manipulation instructions.       tmp19a71   14-2  

 tmp19a71        14.3 pmd components     the two pmd channels are, essentially, functionally equivalent so that only pmd0 is  expla ined here.     14.3.1  three-phase waveform generation circuit    pwm conduction  control  protection  control   dead  time  control  mdprd0  cmpu0  cmpv0  cmpw0  mdcr0  mdout0 u x   v y   w z  emgcr0 mdcr0  emgrel0 intemg0 intpmd0  u x   v y   w z u? x?   v? y?   w? z? pwmu    pwmv    pwmw  pwmsync emg0 mdcnt0  port  control    figure 14.3.1  three-phase waveform generation circuit     the 3-phase waveform generation circuit consists of a pulse width modulation (pwm)  c ircuit, a conduction control circuit, an emg pr otection (emergency stop) circuit and a dead  time control circuit. the pulse width modula tion circuit generates independent 3-phase  pwm waveforms with the same pwm carrie r wave. the conduction control circuit  determines the output pattern for each of the upper and lower sides of the u, v and w  phases. the emg protection circuit enables emergency output stop by emg0 input. the  dead time control circuit prevents a short circuit which may occur when the upper side and  lower side are switched.     tmp19a71   14-3  

 tmp19a71          14.3.2  pulse width modulation circuit (pwm waveform generation unit)      pwm control    ??   xk  imclk  pwm sync clock  pwmsync  pwmu0 pwmv0 pwmw pwm interrupt  intpwm0  mdcr0      15-8   | 7 | 6 | - | - | 3,2,1 | 0 bufferu   bufferv  bufferw  mdprd0  15-0  cmpu0  15-0  cmpv0  15-0  cmpw0  15-0  selector/  latch  selector  0x0001  3 mdcnt0 15-0 up/down pmd control register pwm counter register pwm period register  pwm compare register  pwm counter  to sync sampling signal generation circuit    figure 14.3.5  figure 14.3.2  pulse width modulation circuit    the pulse width modulation circuit has a 16-bit  up-/down-counter  (pwm counter) and  generates pwm carrier waves wi th a resolution of 35.7 ns (imclk = 28 mhz). the pwm  carrier wave mode can be selected from the following two modes:  pwm mode 0   : edge pwm (sawtooth wave modulation)  pwm mode 1  : center pwm (triangular wave modulation)     the mdprd0 register is used to specify the pwm period. the mdprd0 is  dou ble-buffered and the comparator input is updated at every pwm period or at every half  pwm period.                                                                   imclk [hz]    sawtooth wave pwm  : mdprd0 register value =  DDD DDDDDD DD DD                                                      pwm frequency [hz]                                                            imclk  [hz]    triangular wave pwm  :  mdprd 0 register value =  DDDDDDDDDDDDDDD                                                              pwm frequency x 2 [hz]    tmp19a71   14-4  

 tmp19a71          the pulse width modulation circuit compares the pwm compare registers of the 3 phases  (cmpu0, cmpv0, cmpw0) and the carrier  wave generated by the pwm counter  (mdcnt0) to determine which is larger to generate pwm waveforms with the desired  duty.   the pwm compare register of each phase has a compare register (double-buffer  structure ). the pwm compare register value is loaded into the corresponding compare  register at every pwm period (when the internal counter value matches the mdprd0  value). it is also po ssible to update the compare register at every half pwm period.     [sawtooth wave]                      [ triangular  wave]    mdcnt0  time  on    off  pwmu  waveform   [ mdprd0 ]    [ cmpu0 ]  mdcnt0  time  on    off  pwmu  waveform  mdcnt0 counts up to the mdprd0 value  and it is then cleared to 0 in the next cycle.  when up-counting switches to  down-counting, the peak value  (mdprd0) continues for two cycles.    when down-counting switches to  up-counting, the value 1 continues  for two cycles.    [ mdprd0 ]    [ cmpu0 ]    figure 14.3.3  pwm waveforms     three-phase pwm waveforms can be gene rated in the following two modes:    (1) 3-phase independent mode:  each of the pwm compare registers for the three phases is set independently to  g enerate independent pwm waveforms for each phase. this mode is used to generate  drive waveforms such as  sinusoidal waves.      (2) 3-phase common mode:  only the u-phase pwm compare register is set to generate identical pwm  wav eforms for all the three phases. this mode  is used for rectangular wave drive of  brushless dc motors.       tmp19a71   14-5  

 tmp19a71            the pulse width modulation circuit generates pwm interrupt requests in  synchronization with pwm waveforms. the pwm interrupt period can be set to half a  pwm period, one pwm period, two pwm periods, or four pwm periods.     when the pwm interrupt period is set to two or four pwm periods, the first interrupt  aft er the counter is started occurs at any timing  in the specified period. for example, if an  interrupt is to be generated at every four pwm  periods, the first interrupt will be generated  any time during the first to fourth pwm periods with the second and subsequent interrupts  generated at every fourth pwm period.       mdprd0=0x100  0x003 0x002  0x001 0x002 intpmd0       intprd0=0x0       (0.5 period)  0x097 ?? pwm counter           mdcnt0 0x001 pwm period             mdprd0 0x100 0x105 0x098 0x099 0x100 0x105 0x104  0x103  0x102  time mdcnt0  mdprd0=0x105  if the mdprd0 is reloaded during this period, the counter counts up to  the value previously set in the mdprd0 and then starts counting down  from the new value.        figure 14.3.4  mdprd0 reload timing (triangular wave, interrupt at every 0.5 pwm period)       tmp19a71   14-6  

 tmp19a71          pmd0 control register      7 6  5 4  3 2 1  0  mdcr0 bit  sy mbol  updwn  syncen dtymd  pint  intprd  pwmmd pwmen (0xffff_c300)  read/write  r  r/w  r/w  r/w  r/w  r/w  r/w    reset  value  0  0  0  0 0 0  0    function                  15 14  13 12  11  10  9  8   bit  sy mbol  dtr   read/write  r/w    reset value  0x00      symbol  name  function  updwn  pwm counter flag  0: up-counting  1: down-counting  syncen  pmd synchronized start  0: disable synchronized start  1: enable synchronized start   dtymd  duty  mo de  0: 3-phase common mode  1: 3-phase independent mode  pint  pwm interrupt timing  0: interrupt request when pwm counter = 1  1: interrupt request when pwm counter = mdprd   [pwm counter = mdprd when edge mode is selected (pwmmd=0). pwm counter =  1 or mdprd when 0.5 pwm period is selected  (intprd=00).]  intprd  pwm interrupt period  00: interrupt request at every 0.5 pwm period      (pwm mode1: triangular waves only)  01: interrupt request at every pwm period  10: interrupt request at every 2 pwm periods  11: interrupt request at every 4 pwm periods  pwmmd  pwm mode   0: pwm mode 0:  edge pwm (sawtooth waves)   1: pwm mode 1:  center pwm (triangular waves)   pwmen  pwm counter start   0: stop & clear   1: start    note:  the settings in the mdcr0 register must be changed while the pwmen bit is 0. it is also not allowed to change the  mdcr0 se ttings at the same time as writing to the pwmen bit to start or stop the pwm counter.     tmp19a71   14-7  

 tmp19a71            pmd0 count register      15  14  13  12 11 10 9 8  7 6 5  4 3 2  1 0   bit  sy mbol  mdcnt  mdcnt0 read/write  r  (0xffff_c304)  reset value  0x0000    function  pwm counter value: 0x0001 to 0xffff      pmd0 period register      15  14  13  12 11 10 9 8  7 6 5  4 3 2  1 0   bit  sy mbol  mdprd  mdprd0 read/write  r/w  (0xffff_c308)  reset value  0x0000    function  pwm carrier wave period (must be within 0x0010 to 0xffff.)  note:   this register is double-buffered; the value written to this register takes effect when mdcnt0 =  mdprd0.     pmd0 compare registers  (u, v, w)      15  14  13  12 11 10 9  8 7 6  5 4 3  2 1 0  cmpu0 bit  sy mbol  cmpu  (0xffff_c30c)    cmpv  cmpv0   cmpw  (0xffff_c310)  read/write  r/w  cmpw0 reset  value  0x0000  (0xffff_c314)    cmpu0  pwm compare u register  0x0000 to 0xffff: u-phase pulse width duty  cmpv0  pwm compare v register  0x0000 to 0xffff: v-phase pulse width duty  cmpw0  pwm compare w register  0x0000 to 0xfff: w-phase pulse width duty  note 1 :   when cmpx0=0, a 0%-duty cycle waveform is generated. when cmpx0  R  mdprd0, a 100%-duty  cycle waveform is generated.   note 2  :  these registers are double-buffered; the values written to these registers take effect when mdcnt0 =  mdprd0.            tmp19a71   14-8  

 tmp19a71          detailed description of the pmd0 registers  symbol  name  function  updwn  pwm counter flag  indicates whether the pwm  counter is up-counting or do wn-counting. when edge  pwm is selected, this bit is always read as 0.   syncen  pmd synchronized start  enables t he pmd s ynchronized start function.   dtymd  duty mode  selects whether to make duty setting independently for each phase or to use the  cmpu register s etting for all three phases.   pint  pwm interrupt timing  selects whether to genera te an  interrupt when pwm counter equals 1 or the  mdprd value.  intprd  pwm interrupt period  selects the pwm interrupt period from 0.5 pwm period, one pwm period, two pwm  periods and f our pwm periods. if this bi t is changed during operation, an interrupt  may occur at that time.   pwmmd  pwm mode  selects pwm mode 0 (edge pwm, sawtooth wave) or pmw mode 1 (center pwm,  triangular w ave).   pwmen  waveform generation circuit   enable/disable  when this bit is cleared to stop and clear the pwm counter, output ports become  high-impedance.  before setting this bit to 1 to  start the pwm counter, it is necessary  to set all the other bits in the mdcr0 register. while this bit is set to 1, do not change  the mdcr0 settings other than the pwmen bit.  mdcnt  pwm counter  a 16-bit counter for  reading th e pwm period count value.   mdprd  pwm period  a 16-bit register for specifying the pwm period. this register is double-buffered and  can be changed  even when the pwm counter is counting. the buffer is loaded at  every pwm period. (that is, when the pw m counter matches the mdprd value.  when 0.5 pwm period is selected, loading  is performed when the pwm counter  matches 1 or mdprd0.) see figure 14.3.4.  cmpu  cmpv  cmpw  pwm pulse width  16-bit compare registers for determining the output pulse width of u, v and w  phases. these registers are  double-buffe red. pulse width is determined by  comparing the buffer and the pwm counter  to evaluate which is larger.  when  cmpx0 = 0, a 0% duty-cycle waveform is generated. when cmpx0 >= mdprd0, a  100% duty-cycle waveform is generated. (to be loaded when the pwm counter  matches the mdprd value. when 0.5 period is selected, loading is performed when  the pwm counter matches 1 or mdprd.)      setting the syncen bit of the mdcr0 register to 1 enables the pmd synchronized start function.  when the pwmen bit of the mdcr0 is set to 1 with the pmd synchronized start function enabled,  pmd0 is put on standby for starting as soon as th e pwmen bit of the mdcr1 is set to 1 to start pmd1.  by setting the syncen and pwmen bits simultaneously, pmd0 can be put on standby for synchronized  start.   when the synchronized start function is enabled for both pmd0 and pmd1 (mdcr0.syncen=1,  md cr1.syncen=1), the channel that  is enabled first (mdcrx.pwmen  bit=1) is put on standby and  starts operating as soon as the other channel is enabled.     even when the synchronized start function is enabled, registers are set independently for each channel.  t o operate pmd0 and pmd1 with the same conditions, it is necessary to set the pmd0 and pmd1  registers identically.       example: to start pmd0 in synchronization with pmd1    mdcr0 = 0y********_*1*****1    ; s yncen=1 (enable the synchronized start function.)  ; pwmen=1 (put pmd0 on standby.)  mdcr1 = 0y********_*******1    ; pwmen=1 (s tart pmd1.)        tmp19a71   14-9  

 tmp19a71          14.3.3 conduction control circuit    mdout0  u      x            v      y            w      z  pwmu  pwmv  pwmw  pwm sync  imclk  s  selector  6 3 pmd output register  latch  ---  12,11  10,9,8 7,6 5,4,3,2,1,0  2  2 fig.12.3.7   continued   from  fig.12.3.2  continue to   fig. 14.3.6  figure 14.3.5 conduction control circuit       the conduction control circuit performs output  port control according to the settings made  in the pmd output register (mdout0). the mdout0 register bits are divided into two  parts: settings for the  synchronization signal for port output and settings for port output.   the latter part is double-buffered and update timing can be set as synchronous or  asynchronous to pwm.     the output settings for six port lines are made independently for each of the upper and  lo wer phases through the polh and poll bits of the mdout0 register. in addition, the  uoc, voc and woc bits of the mdout0 register are used to select pwm or h/l output for  each of the u, v, and w phases. when pwm output is selected, pwm waveforms are output.  when h/l output is selected, output is fixed to either a high or low level.  table 14.3.1  shows a  sum mary of u-phase port outputs according to  port output and polarity settings in the  mdout0.    tmp19a71   14-10  

 tmp19a71        pmd0 output register      7  6  5 4 3  2 1  0  mdout0  bit  sy mbol  psyns  woc  voc  uoc  (0xffff_c318)  read/write  r/w  r/w  r/w  r/w   reset  value  0  0  0  0     15  14  13  12  11  10  9  8   bit  sy mbol           polh  poll  wpwm  vpwm  upwm    read/write  r  r  r  r/w r/w  r/w r/w  r/w    reset  value  0  0  0 0 0  0 0  0      symbol  name  function  polh  upper phase port polarity  0: low active  1: high active  poll  lower phase port polarity  0: low active  1: high active  wpwm  w-phase pwm output  0: h/l output  1: pwm waveform output  vpwm  v-phase pwm output  0: h/l output  1: pwm waveform output  upwm  u-phase pwm output  0: h/l output  1: pwm waveform output  psyncs  mdout transfer timing   00: async to pwm     01: load when pwm counter    1  10: load when pwm counter = mdprd  11: load when pwm counter = 1 or  mdprd  woc   -phase output  control    voc   -phase output  control  see  table 14.3.1 .  uoc   -phase output  control    note 1:  before changing the polh, poll and psyncs bits of  the mdout0 register, make sure that the mdcr0.pwmen bit  is cleared to 0.    note 2:  the xpwm and xoc bits of the mdout0 register are  do uble-buffered; the values written to these bits take effect  according to the timing selected in the mdout0.psyncs field.         tmp19a71   14-11  

 tmp19a71            table 14.3.1   s ummary of u-phase port outputs according to the uoc and upwm settings                  polarity: active hi gh (polh, poll=1                     polarity: active low (polh, poll=0)  mdout0  mdout0  mdout  0: h/l output  1: pwm output  mdout  0: h/l output  1: pwm output  bit 1  bit 0  u output x output  u output x output bit 1  bit 0  u output  x output  u output x output 0 0  l  l    DDDDD pwm pwm 0 0  h  h  pwm   DDDDD pwm 0 1  l  h  l  pwm 0 1  h  l  h    DDDDD pwm 1 0  h  l  pwm l  1 0  l  h    DDDDD pwm h  1 1  h  h  pwm   DDDDD pwm 1 1  l  l    DDDDD pwm pwm the voc and vpwm bits and the woc and wpwm bits should be set for the v phase and the w phase, respectively, as shown in the  above table.     name  symbol  function  output port polarity  poll,  polh  select the output port polarity for the upper and lower phases. set these bits  w hen mdcr0.pwmen=0.  port output sync setting  psyncs    select port output timing for the u, v and w phases. select either mdcnt0  (pmd0 comp are register) peak/bottom sync or async.   u-, v-, w-phase output  control  uoc, voc, woc,  upwm, vpwm, wpwm specify port output settings for the u, v and w phases (see  table 14.3.1 ).      tmp19a71   14-12  

 tmp19a71          14.3.4  emg protection circuit    emg protection  control  emgcr0   - - - - - | 2 | 1 | 0  u x v y w z emgrel0  7,6,5,4,3,2,1,0  pemg0   intemg0 u?     x?     v?     y?     w?     z? 3  8 emg control register emg release register emg signal from emg  port  emg interrupt request    pwm  continued from  figure 12.3.5  to continue to  figure 12.3. 7  figure 14.3.6 emg protection circuit     the emg protection circuit is activated when the emg input from the emg0 (pa6) pin  becomes the active state specified in the port a emg control register (paecr). when the  pa6 pin is not configured as an emg input pin, the emg protection circuit does not  function.   the emg protection circuit offers an emergency stop mechanism: when the emg input  is asserted, an emg int errupt request  (intemg0) is generated and the pmdtrg0  output to the ad converter is disabled.   when only the pmd is protected with the emg input pin enabled, all six port output  lin es output inactive signals.     emg protection is set through the emg control register (emgcr0). a read value of 1 in  the emgst bit of th e emgcr0 indicates that th e emg protection circuit is active. in this  state, emg protection can be released by setting all the port output lines inactive  (mdout[10:0]= 00000000000) and then setting the emgrs bit of the emgcr0 to 1.   to disable the emg protection function, the following sequence of operations must be  per formed consecutively. this sequence becomes invalid if it is interrupted by any  operation on the emgcr0 or emgrel0 register before it is completed.       1)   write 0x5a in the emgrel0 register.   2)   write 0xa5 in the emgrel0 register.  3)   clear the emgen bit of the emgcr0 register to 0.     if protection is released in the emg prot ect ion circuit while the emg input pin is  asserted, protection is applied again. for de tails about the port settings related to the  emg protection function, see section 8.12 notes on using the emg input pins (pa6, pa8).              tmp19a71   14-13  

 tmp19a71          emg0 release register      7  6 5 4  3 2 1  0   bit  sy mbol  emgrel  emgrel0 read/write  w  (0xffff_c31c)  reset value  0x00    function  the emg protection circuit can be disabled by writing 0x5a and 0xa5 in this order to this register   and then clearing emgcr0.emgen bit to 0.    emg0 control register      7  6 5 4  3 2 1  0   bit  sy mbol                 emgst  emgrs  emgen emgcr0  read/write  r  r r r  r r  w  r/w  (0xffff_c320)  reset  value  0  0 0 0  0 0 0  1      symbol  name  function  emgst  emg protection state   0:  DD    1: protected  emgrs  emg protection release   0:  DD    1: release protection  emgen  emg protection circuit   enable/disable   0: disable   1: enable    detailed description of the emg control register  name  symbol  function  emg protection state  emgst  the emg protecti on st ate can be known by reading this bit.   emg protection release  emgrs  emg  protection  can be released by setti ng mdout[10:0] to 00000000000 and then  setting the emgrs bit to 1.   emg protection circuit  enable/disable  emgen  the emg protection circuit is enabled by setting this bit to 1. in the initial state, the  emg prot ection circuit is enabled.   to disable this circuit, write 0x5a and 0xa5  in this  order to the emgrel0 register  and then clear the emgen bit to 0.         tmp19a71   14-14  

 tmp19a71        14.3.5  dead time control circuit    mdcr0   15  8 | - | - | - | - | - | - | - | - u      x  imclk  v?  y?  on delay  circuit  on delay  circuit  on delay  circuit  w?  z?  u?  x?  v      y  w      z  output polarity switching unit  dead time unit mdout0  pmd output register  ---12,1 1 -,-,- -,- -,-,-,-,-,-  pmd control register 1/2  continued from  figure 14.3.6    figure 14.3.7  dead time control circuit     the dead time control circuit consists of  a dead time unit and an output polarity  switching unit.   for each of the u, v, and w phases, the on  d elay circuit introduces a delay (dead time)  when the upper and lower phases are switched  to prevent a short circuit. the dead time is  set to the dtr field in the mdcr0 register as an  8-bit value with a resolution of 71.4 ns (at  imclk = 28 mhz). no delay time is inserted when dtr=0x00.   the output polarity switching unit allows the polarity (active high or active low) of the  upp er and lower phases to be independently set through the polh and poll bits of the  mdout0 register.   pmd0 control register      7 6 5 4  3 2  1  0  mdcr0 bit  sy mbol  updwn  -  dt ymd pint  intprd  pwmmd pwmen (0xffff_c300)  read/write  r  r/w r/w r/w  r/w  r/w  r/w    reset  value  0 0 0 0  0  0  0    function   must be set  to 0.                15 14 13 12  11  10  9  8   bit  sy mbol  dtr   read/write  r/w    reset value  0x00   function  dead time: 71.4 ns  8 bits (max. 18.2   s  imclk = 28 mhz    tmp19a71   14-15  

 tmp19a71            14.3.6  sync sampling signal generation circuit    mdcnt0  trgcmp00  pmdtrg01  pmdtrg00  trgcmp01  3-phase waveform generation circuit ad converter control circuit tbuf00  tbuf01  trgcr0  pwm sync signal pwm sync  pwm sync  pmdtrg02  trgcmp02  tbuf02  pwm sync    slope  selection    figure 14.3.8  sync sampling signal generation circuit    the sync sampling signal generation circuit  gen erates trigger sign als for starting adc  sampling in synchronization with pwm. the  adc trigger signal (pmdtrg0) is generated  by a match between the mdcnt0 and trgcmp0.  the signal generation timing can be  selected from up-count match, down-count match, and up-/down-count match. when the  edge pwm mode is selected, the adc trigger signal is generated on an up-count match.  when pwm output is disabled (mdcr0.pwmen=0 ) or emg protection is applied, trigger  output is also disabled.       tmp19a71   14-16  

 tmp19a71          trigger control register (pmd0)      15  14  13  12 11 10 9 8 7  6 5 4  3 2 1  0   bit  sy mbol               trg2md  trg1md  trg0md  trgcr0  read/write  r r r  r r r  r  r/w  r/w  r/w  (0xffff_c324)  reset value  0 0 0  0 0 0  0  000  000  000        symbol  name  function  trg2md  pmdtrg2 mode setting  trg1md  pmdtrg1 mode setting  trg0md  pmdtrg0 mode setting  000: trigger output disabled  001: trigger output on down-count match  010: trigger output on up-count match  011: trigger output on up-/down-count match  100: trigger output at pwm carrier peak  101: trigger output at pwm carrier bottom  110: trigger output at pwm carrier peak/bottom  111:   DD   note:  the trg0md, trg1md and trg2md fields must be set while mdcr0.pwmen=0.      trigger compare registers (pmd0)      15  14  13  12 11 10 9 8 7  6  5  4 3  2  1  0  trgcmp02  bit symbol  D   (0xffff_c330)  read/write  r/w  trgcmp01  reset value  0x0000  (0xffff_c32c)  function  pmdtrg0 is output on a match between this register and mdcnt0.   trgcmp00     (0xffff_c328)      note1:  the trigger compare registers  must be set to satisfy the following conditions:  1    rgcmp00, trgcmp01, trgcmp02   mdprd0  note 2: these registers are double-buffered; the values written to these registers take effect at the following  timi ngs:  trgxmd=001: the register values take effect when mdcnt0=mdprd0.  trgxmd=010: the register values take effect when mdcnt0=0.  trgxmd=011: the register values take effect when mdcnt0=mdprd0 or 0.          tmp19a71   14-17  

 tmp19a71        15.  encoder input circuit    15.1 functional overview  (1)   allows direct input of the incremental encoder signal.   (2)   co ntains a x4 multiplier circuit and  a rotation direction control circuit.  (3)   conta ins an absolute position detection counter.  (4)   gen erates an interrupt on a match with the encoder pulse position set value.  (5)   incorp orates noise filters in the signal input part.                    noise filter      select      decoder    interrupt  request  control  interrupt request  intenc  enca  encb  encz  noise filter  noise filter    figure 15.1.1  block diagram of the encoder input circuit    note:  unless otherwise specified, the registers for the encoder input circuit must be accessed as a 16-bit  quantity. bit manipulation instructions cannot be used on these registers.        tmp19a71   15-1 

 tmp19a71          15.2 register description    encoder input control register      7 6 5 4  3  2  1  0  entncr  bit symbol  zen cunen  nr1  nr0  encap           (0xffff_c400)  read/write  r/w    reset value  0 0  00  0  0  0  0      15 14 13 12  11  10  9  8    bit symbol  enclr u/d  zdet                   read/write  w r    reset value  0 0 0 0  0  0  0  0      symbol  name  function  enclr  encoder pulse counter clear  writing a 1 and then a 0 to this bit clears the encoder counter.   u/d  encoder rotation direction  1: cw  0: ccw  zdet  phase z detection state  1: phase z is detected.  0: the cunen bit is set to 1 or a reset is applied.  zen  counter clear by phase z  1: enable  0: disable  cunen  encoder pulse counter enable  1: enable  0: disable  nr[1:0]  noise filter  00: no filter  01: eliminate pulses of less than 31/imclk as noise  10: eliminate pulses of less than 63/imclk as noise  11: eliminate pulses of les than 127/imclk as noise  encap  encoder interrupt request enable 1: enable  0: disable  note 1:  the entncr register must be set after all the other relevant registers have been set.   note 2:  do not change the settings in this register other the enclr and cunen bits while the encoder counter is operating.   note 3:  if the cunen bit is cleared to 0 when encnt=enint, the intenc interrupt is generated.  note 4:  to re-enable the encoder counter after disabling it by cunen=0, clear the counter value by using the enclr bit.        tmp19a71   15-2 

 tmp19a71          t able 15.2.1 detailed description of the encoder input control register   name  symbol  function  encoder pulse counter clear  enclr  writing a 1 and then a 0 to th is bit  clears the encoder counter to 0. then, the counter  starts counting again.   encoder rotation direction  u/d  when the motor is rotati ng in c w direction (phase a of the incremental encoder  signal is 90 degrees ahead of phase b), this bit is set to 1. when the motor is rotating  in ccw direction (phase a is 90 degrees behind  phase b), this bit is cleared to 0.   z phase detection state  zdet  this bit is cleared to 0 when a 1 is written to the cunen bit and at reset. it is set to 1  on the next  zdetect?the signal to be output on the rising edge (cw direction) or  falling edge (ccw direction) of the increm ental encoder signal phase z. (this bit is  independent of the zen value.)   counter clear by phase z  zen  when the motor is rotating in cw   direction, this bit is cleared to 0 on the rising edge  of phase z (zdetect). when the motor is ro tating in ccw direction, this bit is  cleared to 0 on the falling edge of phase z (zdetect). if enclk (a clock obtained  by multiplying the phase a and phase b signals by 4) and zdetect coincide with  each other, the counter is cleared to 0 without counting.   encoder pulse counter enable  cunen  when cunen=1, the zdet  bit is cleared to 0 and the encoder cou nter (encnt) is  enabled. when cunen=0, the encoder  counter is disabled.   noise filter  nr1,0  00: no filter  01: eliminate pulses of less than 31/imclk as noise (1.11   s imclk = 28 mhz)   10: eliminate pulses of less than 63/imclk as noise (2.25   s imclk = 28 mhz)   11: eliminate pulses of less than 127/imclk as noise (4.54   s imclk = 28 mhz)  encoder interrupt request  encap  encap=1 enables interrupt  requ est signal generation. e ncap=0 disables interrupt  request signal generation.      tmp19a71   15-3 

 tmp19a71              encoder counter reload register      15 14  13  12  11 10 9 8 7  6 5 4  3 2 1  0  enreload  bit symbol     (0xffff_c404) read/write  r/w   reset  value  0x0000    function  encoder counter target value: 0x0000 to  0 xffff (input pulse count multiplied by 4)  when phase z is used: set the number  of pulses r equired for one rotation  when phase z is not used: set the number of   pulses required for one rotation minus one      when the encoder counter (encnt) is up-counting, the counter is zero-cleared on the next enclk  tim ing after the count value reaches the enreload value. when the encoder counter (encnt) is  down-counting, it is re-loaded with the enreload  value on the next enclk timing after the counter  value reaches 0.     encoder compare register      15  14  13  12 11 10 9  8 7  6 5 4  3 2 1  0  enint  bit symbol     (0xffff_c408)  read/write  r/w     reset value  0x0000    function  interrupt request generation position: 0x0000 to 0xffff  when the encoder counter matches the value set in  this register , an interrupt request is generated.       when the encoder counter (encnt) value reaches th e  enint value, an interrupt request (intenc )  is generated. when zen=1, however, an interrupt requ est is not generated until the zdet bit is set to 1.       encoder counter      15 14  13  12 11 10 9  8 7 6  5 4 3  2 1 0  encnt  bit symbol     (0xffff_c40c)  read/write  r     reset value  0x0000    function  0x0000 to 0xffff: up-/down counter that counts encoder pulses       when the motor is rotating in cw direction, the enco d er counter is an up-counter to be zero-cleared on  the next enclk timing after the count value reaches  the enreload value. when the motor is rotating  in ccw direction, the encoder counter is a down-co unter to be re-loaded with the enreload value on  the next enclk timing after the count value reaches 0.       tmp19a71   15-4 

 tmp19a71          15.3 operation    phase a input enca  cw ccw  motor rotation direction rotation direction state u/d  phase b input encb  phase z input encz  encoder pulse  enclk  phase z detection  zdetect  encoder counter  encnt  0x100 0x101  0x0 0x1 0x2 0x3 0x2 0x1  0x1 0x0 0x0  0x5db 0x5da initial rotation (zdet=0)  intenc  enint=0x2  0x4 ?? ??    figure 15.3.1  encoder input circuit timi ng ch art (1) (zen=1, enreload=0x05db)    phase a input enca  cw ccw  motor rotation direction  rotation direction state  u/d  phase b input encb  encoder pulse  enclk  counter clear  encoder counter  encnt  0x100 0x101  0x0 0x102 0x1 0x103 0x2 0x1  0x1 0x0 0x0  0x5db 0x5da  intenc  enint=0x2  0x2 ?? ?? set enclr  set enclr        figure 15.3.2   encoder input circuit timing chart (2) (zen=0, enreload=0x5db)     tmp19a71   15-5 

 tmp19a71            (1)   each incremental encoder signal is connected to phase a, phase b, and phase z, respectively. this  signal is multiplied by four for being counted.   (2)   when the motor is rotating in cw direction (phase a is 90 degrees ahead of phase b), the encoder  count er operates as an up-counter. when the  count value reaches the enereload value, the  counter is zero-cleared on the next enclk timing for counting up.   (3)   when the motor is rotating in ccw direction  (phas e a is 90 degrees behind phase b), the encoder  counter operates as a down-counter. when the count value reaches 0, the counter is re-loaded  with the enreload value on the next enclk timing for counting down.   (4)   when zen=1, the encoder counter is zero-cleared on the rising edge of phase z (zdetect) while  the m otor is rotating in cw direction and on the falling edge of phase z (zdetect) in the case of  ccw direction. when enck and zdetect coincide with each other, no count operation is  performed and the counter is zero-cleared.     (5)   when a 0 is written to the enclr bit, the counter is zero-cleared.   (6)   an interrupt request can be generated when the counter value reaches the enint value. when   zen=1, h owever, an interrupt request cannot be  generated until the zdet bit is set to 1.   (7)   the zdet bit is zero-cleared when a 1 is writte n to the cu nen bit and at reset, and it is set to 1  on the next zdetect timing (regardless of the zen value).   (8)   the u/d bit is set to 1 when cw rotation is  d etected and to 0 when ccw rotation is detected.         tmp19a71   15-6 

 tmp19a71        15.4  how to use the encoder input circuit  15.4.1  using the encoder interrupt request  (1) set the encoder pulse count.   assuming that the encoder requires 1200 pulses for one rotation, the pulse count (after  be ing multiplied by 4) is set as follows:       enreload=1200x4=0x12c0  0 0 0 1  0 0 1  0 1  0  1 1 1  1 1 1    (2) set the encoder compare register value.  for generating an interrupt request at counter value = 1000 (03e8 h ), the encoder  compare register is set as follows:      enint=0x03e8  0 0 0 0  0 0 1  1 1  1  1 0 1  0 0 0    (3) enable the encoder counter, interrupt request, and z-phase detection.       15 14 13  12  11  10 9 8 7 6 5 4 3 2 1 0 entncr  - - -  -  -  -  - -   --  ---   (4) operation  1.  as the encoder rotates, the encoder deco de r outputs x4 pulses (enclk) and rotation  direction (u/d).   2. the encoder counter counts enclk pulses. whether to count up or down is  det ermined by rotation direction.  3.  when phase z is detected, the encoder counter  is cleared. in th e  case of up-counting,  when the count value matches the enreload register value, the counter is  zero-cleared on the next enclk timing. in the case of down-counting, when the  count value reaches 0, the counter is re -loaded with the enreload register value  on the next enclk timing.  4. up to the first z-phase detection, the encoder counter value indicates not the  absolut e position of the actual encoder but th e relative position from count start time.  when phase z is detected, the zdet is set to 1 and the counter value now indicates  the absolute position.  5.  when a match occurs between the encode r compar e register (enint) value and the  encoder count value and the zdet is set to 1, an enint interrupt request is  generated. this interrupt request is ge nerated regardless whether the counter is  counting up or down.              tmp19a71   15-7 

 under development  tmp19a71        16. rom correction   this chapter describes the rom correctio n function supported by the tmp19a71.    note:  the registers for the rom correction function must be accessed as a 32-bit quantity. bit manipulation  instructions cannot be used on these registers.      16.1 features  up to eight 8-word sequences  of data can be replaced.   ?   ?   ?   ?   when the physical address stored in an  address register  (a ddregn) matches the  program counter (pc) value or the address ge nerated by the dmac (the lower five bits  of the address are ?don?t care?), the data at the specified address in the on-chip rom is  replaced with the data from the ram area corresponding to the address register.   writing an address to an address register  caus es rom correction for the address to be  enabled automatically.  a reset is required  to disable the rom correction function.   a correction requiring the replacement of mo r e than eight words can be performed by  replacing the rom data with an instruction code which makes a branch to a specified  location in the ram area which contains substitution data.   16.2 operation  to correct data in a rom area (or a projected rom area), store the physical address of the  area in an address register (addregn). store the substitution data in the ram area  corresponding to the address register. writing an  address to an addre ss register causes rom  correction for the address to be enabled automati cally. upon reset, the rom correction function  is disabled. if the initial routine executed upon reset is used to correct rom data, write  a  physical address  to the relevant address register after  a reset is released.  the address registers  to which addresses are written are enabled for rom correction. when the stored address  matches the pc value (if the tx19a core processor owns the bus) or the source or destination  address issued by the dmac (if the dmac owns the bus), the data at the specified address in  the rom is replaced with the data stored in the corresponding ram area.  for example, storing  addresses in the addreg0 and addreg3 enables correction for the respec tive rom areas, so  that the rom correction circuit block constantly  monitors the pc and  dmac-issued addresses  for a match with a specified address and, if a ma tch is detected, replaces data, while ignoring  the addreg2 and addreg4 to addreg7. each a ddress register has bits  31:5 although only  bits 17:5 are used for address comparison, in order to simplify the circuit. a match detected in  the rom correction circuit is internally anded with the romcs signal, which indicates a  specified rom address block, to determine an  exact match. rom a ddresses specified for  correction must be located on ei ght-word boundaries, i.e., the lower five bits are 0. in other  words, rom data is always replaced in 32-byte  units. if only part of 32 bytes needs to be  replaced, substitution ram data corresponding to the other bytes must be the same as the  current data in the corresponding rom addresses.         txmp9a70   16-1 

 tmp19a71          the following table shows the relationship between the address registers and ram areas.     table 16.2.1 relationship between t he  addregn registers and ram areas  address register  ram area  addreg0  0xffff_bf00  to   0xffff_bf1f  addreg1   0xffff_bf20 to 0xffff_bf3f  addreg2  0xffff_bf40  to   0xffff_bf5f  addreg3  0xffff_bf60  to   0xffff_bf7f  addreg4  0xffff_bf80  to   0xffff_bf9f  addreg5  0xffff_bfa0 to 0xffff_bfbf  addreg6  0xffff_bfc0 to 0xffff_bfdf  addreg7  0xffff_bfe0 to 0xffff_bfff      tx19a core processor compare circuit address registers addregx converter ram rom g-bus compare  enable compare  address [17:5] load/fetch  address [17:5] ramcs signal romcs signal ram data rom data conversion  address address conversion  enable                                                                         figure 16.2.1  rom corr ection block diagram    tmp19a71   16-2 

 under development  tmp19a71        16.3 registers  (1) address registers      7  6 5  4 3 2  1 0  addreg0  bit symbol  add07  add06  add05                 (0xffff_e540)  read/write  r/w    reset value  0  0 0  1 1 1  1 1   function                    15  14  13  12  11 10  9  8   bit  sy mbol  add015  add014 add013 add012 add011 add010  add09  add08  read/write  r/w    reset value  0  0 0  0 0 0  0 0   function                    23  22 21  20 19 18  17 16   bit  sy mbol  add023  add022 add021 add020 add019 add018  add017  add016  read/write  r/w    reset value  0  0 0  0 0 0  0 0   function                      31  30 29  28 27 26  25 24   bit  sy mbol  add031  add030 add029 add028 add027 add026  add025  add024  read/write  r/w    reset value  0  0 0  0 0 0  0 0   function                         7  6 5  4 3 2  1 0  addreg1  bit symbol  add17  add16  add15                 (0xffff_e544)  read/write  r/w    reset value  0  0 0  1 1 1  1 1   function                    15  14  13  12  11 10  9  8   bit  sy mbol  add115  add114 add113 add112 add111 add110  add19  add18  read/write  r/w    reset value  0  0 0  0 0 0  0 0   function                    23  22 21  20 19 18  17 16   bit  sy mbol  add123  add122 add121 add120 add119 add118  add117  add116  read/write  r/w    reset value  0  0 0  0 0 0  0 0   function                      31  30 29  28 27 26  25 24   bit  sy mbol  add131  add130 add129 add128 add127 add126  add125  add124  read/write  r/w    reset value  0  0 0  0 0 0  0 0   function                             txmp9a70   16-3 

 tmp19a71                  7  6 5  4 3 2  1 0  addreg2  bit symbol  add27  add26  add25                 (0xffff_e548)  read/write  r/w    reset value  0  0 0  1 1 1  1 1   function                    15  14  13  12  11 10  9  8   bit  sy mbol  add215  add214 add213 add212 add211 add210  add29  add28  read/write  r/w    reset value  0  0 0  0 0 0  0 0   function                    23  22 21  20 19 18  17 16   bit  sy mbol  add223  add222 add221 add220 add219 add218  add217  add216  read/write  r/w    reset value  0  0 0  0 0 0  0 0   function                      31  30 29  28 27 26  25 24   bit  sy mbol  add231  add230 add229 add228 add227 add226  add225  add224  read/write  r/w    reset value  0  0 0  0 0 0  0 0   function                         7  6 5  4 3 2  1 0  addreg3  bit symbol  add37  add36  add35                 (0xffff_e54c)  read/write  r/w    reset value 0  0 0  1 1 1  1 1   function                    15  14  13  12  11 10  9  8   bit  sy mbol  add315  add314 add313 add312 add311 add310  add39  add38  read/write  r/w    reset value 0  0 0  0 0 0  0 0   function                    23  22 21  20 19 18  17 16   bit  sy mbol  add323  add322 add321 add320 add319 add318  add317  add316  read/write  r/w    reset value 0  0 0  0 0 0  0 0   function                      31  30 29  28 27 26  25 24   bit  sy mbol  add331  add330 add329 add328 add327 add326  add325  add324  read/write  r/w    reset value 0  0 0  0 0 0  0 0   function                     tmp19a71   16-4 

 under development  tmp19a71              7  6  5 4 3  2 1 0  addreg4  bit symbol  add47  add46  add45                 (0xffff_e550)  read/write  r/w    reset value  0  0  0 1 1  1 1 1   function                   15  14  13  12  11  10  9  8   bit  sy mbol  add415  add414 add413 add412 add411 add410  add49  add48  read/write  r/w    reset value  0  0  0 0 0  0 0 0   function                    23  22  21 20 19  18 17 16    bit symbol  add423  add422 add421 add420 add419 add418 add417 add416  read/write  r/w    reset value  0  0  0 0 0  0 0 0   function                      31  30  29 28 27  26 25 24    bit symbol  add431  add430 add429 add428 add427 add426 add425 add424  read/write  r/w    reset value  0  0  0 0 0  0 0 0   function                          7  6 5  4 3 2  1 0  addreg5  bit symbol  add57  add56  add55                 (0xffff_e554)  read/write  r/w    reset value  0  0 0  1 1 1  1 1   function                    15  14  13  12  11 10  9  8   bit  sy mbol  add515  add514 add513 add512 add511 add510  add59  add58  read/write  r/w    reset value  0  0 0  0 0 0  0 0   function                    23  22 21  20 19 18  17 16   bit  sy mbol  add523  add522 add521 add520 add519 add518  add517  add516  read/write  r/w    reset value  0  0 0  0 0 0  0 0   function                      31  30 29  28 27 26  25 24   bit  sy mbol  add531  add530 add529 add528 add527 add526  add525  add524  read/write  r/w    reset value  0  0 0  0 0 0  0 0   function                                   txmp9a70   16-5 

 tmp19a71                7  6  5 4 3  2 1 0  addreg6  bit symbol  add67  add66  add65                 (0xffff_e558)  read/write  r/w    reset value  0  0  0 1 1  1 1 1   function                   15  14  13  12  11  10  9  8   bit  sy mbol  add615  add614 add613 add612 add611 add610  add69  add68  read/write  r/w    reset value  0  0  0 0 0  0 0 0   function                    23  22  21 20 19  18 17 16    bit symbol  add623  add622 add621 add620 add619 add618 add617 add616  read/write  r/w    reset value  0  0  0 0 0  0 0 0   function                      31  30  29 28 27  26 25 24    bit symbol  add631  add630 add629 add628 add627 add626 add625 add624  read/write  r/w    reset value  0  0  0 0 0  0 0 0   function                          7  6  5 4 3  2 1 0  addreg7  bit symbol  add77  add76  add75                 (0xffff_e55c)  read/write  r/w    reset value  0  0  0 1 1  1 1 1   function                   15  14  13  12  11  10  9  8   bit  sy mbol  add71 5  add714 add713 add712 add711 add710 add79  add78  read/write  r/w    reset value  0  0  0 0 0  0 0 0   function                    23  22  21 20 19  18 17 16   bit  sy mbol  add72 3  add722 add721 add720 add719 add718 add717 add716  read/write  r/w    reset value  0  0  0 0 0  0 0 0   function                      31  30  29 28 27  26 25 24   bit  sy mbol  add73 1  add730 add729 add728 add727 add726 add725 add724  read/write  r/w    reset value  0  0  0 0 0  0 0 0   function                    note:  dma transfer cannot be performed to an address register.  dma transfer can be performed to a data  area in th e ram which contains substitution data. the rom correction function can be used when  either the tx19a core processor or dmac owns the bus.     tmp19a71   16-6 

 tmp19a71          17. flash memory  this chapter describes the hardwa re configuration and operation of  the flash memory contained in  the tmp19a71.     17.1 overview  17.1.1 features  1) memory capacity  the tmp19a71 contains 2 mbits (256 kbytes) of flash memory, which is divided into two  128-kbyte blocks. each block can be independently protected from program and erase  operations. while the tx19a core processor can access the flash memory through a full  32-bit data bus, an external flash programme r can only access the flash memory through  a 16-bit data bus.     2)  program and erase times  c hip program time (including  verify): 5 seconds (typ.)  chip erase time (including verify): 20 seconds (typ.)    note:  these program and erase times are typical val ues not including data trans fer overhead. the actual  chip program and erase times depend on the programming method used.     3) programming modes  the tmp19 a71 flash memory can be programmed while mounted on a user board  (on-board programming mode) or by using an eprom programmer (programmer mode).   ?   on-board programming modes                1) user boot mode        a user-created programming algorithm can be used.     2) single boot mode        a toshiba-defined serial interface protocol is used.  ?  programmer mode             a general-purpose programmer can be used. (t. b. d)        5)   pro gramming method  programming operations of the tmp19a71 fl ash memory are controlled by commands  except for a few functions.  the tmp19a71 contains a command sequencer which  recognizes programming commands and automatically executes corresponding sequences  of operation. this feature eliminates the need for the user to code complex program and  erase sequences.     the tmp19a71 provides an anti-programmer security feature for protecting the on-chip  f lash memory from being read by programmi ng equipment. the tm p19a71 also allows  the user to protect individual blocks of the flash memory from program or erase  operations. this block protection feature is implemented by software; the hardware  method (high voltage application) is not supported. the anti-programmer security  feature is automatically enabled when both of the two blocks are placed under protection.  when the unprotect command is executed, the flash memory is automatically erased  before block protection is lifted to ensure data security.      tmp19a71   17-1  

 tmp19a71          table 17.1.1 modified/deleted auto programming features  available auto programming features  modified/deleted features  ?  auto program  ?  auto chip erase  ? auto block erase  ? auto multi-block erase  ? data polling    modified: block protection is avai lable onl y under software control.    deleted: erase resume/suspend mode     17.1.2 block diagram      internal address bus  rom controller  mode setting  internal signal  control  a ddress data flash memory  column decoder/sense amp data latch address latch erase block decoder          control  logic      command  sequencer rdy/bsy output  internal data bus  internal control bus      flash memory array    256 kb         row decoder  mode control                                                                 figure 17.1.1   fla sh memory block diagram    tmp19a71   17-2  

 tmp19a71        17.2 operating modes  the tmp19a71 offers a total of four operating modes as shown in the table below.     table 17.2.1   ope rating modes  operating mode  description  single-chip mode        normal mode          user boot mode  after a reset, the tx19a core processor exec utes o ut of the on-chip flash memory.         single-chip mode is further divided into normal m ode in  which the user applic ation executes and user  boot mode which allows for re-programming of the flash memory while the tmp19a71 is installed on a  printed circuit board.     the user can freely define how to switch between no rmal mode and user boot mode. for example, the  logic  state on port 00 can be used to determine whether to put the flash memory in normal mode or user  boot mode. in this case, the user must include a routi ne in the application program to test the state of that  port.  single boot mode  after a reset, the tx19a core processor exec utes out of the on-chi p boot rom (which is a mask rom).  the boot rom contains a routine to aid users in pe rforming on-board programming of the flash memory  via a serial port of the tmp19a71. the serial port  is connected to an external  host which transfers new  data according to a prescribed protocol.   programmer mode  this mode allows for re-programming of the flash memory with a general-purpose eprom programmer. use the prog rammer and programming adaptor recommended by toshiba.     the on-chip flash memory can be programmed in one of the following three modes: user boot  m ode, single boot mode and programmer mode. of these modes, user boot mode and single boot  mode allow the flash memory to be programmed while the tmp19a71 is mounted on a printed  circuit board. these two modes are collectively  referred to as on-board  programming modes.       tmp19a71   17-3  

 tmp19a71          the logic states on the test0, p90 to p93 an d p94 (boot) pins during a reset sequence  determine the mode of operation for the flash memory, as shown in  table 17.2.2 . after the reset  state is r eleased, p94 (boot) and p90 to p93 ca n be configured as general-purpose i/o pins.     after a reset, the tx19a core processor operates in compliance with the selected mode. when  p rogrammer mode is selected, however, the reset pin must be held at logic 0. the input pins  listed in  table 17.2.2  must remain stable once the flash memory is put in a given mode of  op eration.     table 17.2.2   mod es of operation  input pins    operating mode  reset  p90  p91 p92 p93  boot test0  test1  (1)  single-chip mode  0    1  (note ) (note ) (note ) (note ) 1 0  0  (2)  single boot mode  0    1  (note ) (note ) (note ) (note ) 0 0  0  (3)  programmer mode   0  1  1  0  0  (note ) 1 0  note: don?t care. the pins must be held at 0 or 1.             programmer  mode  on-board  programming mode reset = 0  reset = 0  (2) (3) (1)  single-chip mode  reset  a ny condition other than (3)      reset = 0  normal mode  user boot  mode  single boot  mode  user-defined  condition                                  parenthesized numbers indicate that the relevant pins  are at the logic states shown in table 17.2.2.  figure 17.2.1   mode transitions    17.2.1 reset operation  to reset the tmp19a71, the reset input must be  kept at logic 0 at least for 10 ms after  power-up.     tmp19a71   17-4  

 tmp19a71        17.2.2 memory maps  the memory map for the tmp19a71 varies according to the mode of operation selected for  the on-chip flash memory, as shown below.                                                             note: the addresses shown above are physical addresses.       figure 17.2.2   tmp19a71 memory map s      when the tmp19a71 is started in single boot mode, the boot rom (mask rom) is  m apped to an 8-kbyte area starting from the reset vector (0x1fc0_0000), and the flash  memory is mapped from 0x4000_0000.    when the tmp19a71 is started  in s ingle-chip mode, the flash memory is mapped from the  reset vector, and the flash memory sh adow is mapped from 0x4000_0000.    the following descriptions use virtua l addresses,  unless  otherwise noted.      on-chip  peripherals  single-chip mode  single boot mode  programmer mode  0xffff_ffff  0xc000 _0000  0xffff_ffff   0xffff_bfff 0xffff_9800 0xff3f_ffff 0xff20_0000 0x0000_0000 0xff00_0000 0xbf00_0000 0xffff_ffff   0xffff_bfff 0xffff_9800 0xff3f_ffff 0xff20_0000 0xc000_0000 0xff00_0000 0xc000_0000 0x4003_ffff 0x4000_0000 0x1f c3_ffff   0x1fc0_0000 0x2000_0000 on-chip ram (10kb) (reserved)  used for debugging  (reserved)  (reserved)    (reserved)    on-chip rom  shadow  inaccessible   (512 mb)    user program area  maskable interrupt  area  exception vector  area      boot  mrom  (  kb)    inaccessible   (512 mb)  on-chip  flash rom  (reserved)  (reserved)  (reserved)  used for debugging (reserved)  on-chip ram  on-chip  peripherals  on-chip   flash rom  inaccessible   inaccessible  (512 mb)  inaccessible  inaccessible  0x1fc0_1fff 0x4003_ ffff 0x4000_0000 0x2000_0000 0x1fc0_0000 0x0000_0000 0xbf00_0000 0x4000_0000  0x2000_ 0000  0x0003_ffff  0x0000_0000    tmp19a71   17-5  

 tmp19a71          as shown in figure 17.2.3, the tmp19a71 flash memory is comprised of two 128-kbyte  blocks.     block 0 block 1 128kb 128kb 256kb      figure 17.2.3   fla sh memory block architecture    table 17.2.3   bl ock addresses based on mode setting    single-chip mode  single boot mode  programmer mode  block 0  0xbfc0_0000  to 0xbfc  _fff f  (shadow: 0x0000_0000  to 0x0001_ffff)  0x0000_0000 to 0x000  _f fff 0x0000_0000 to 0x0001_ffff block 1  0xbfc2_0000 to 0xbfc3_ffff  (shadow: 0x0002_0000  to 0x0003_ffff)  0x0002_0000 to 0x0003_ffff   0x0002_0000 to 0x0003_ffff 17.2.3 block protection  the tmp19a71 flash memory is comprised of tw o 128-kbyte blocks. to protect stored data  from any program and erase operations, each block has a protect bit, which can be set by  executing the block protect command sequence. blocks in protection mode are protected  from even the chip erase and multi-block  erase commands; these commands erase only  unprotected blocks. since protection status is st ored in flash memory cells, it is retained if  the chip is powered off. when both blocks are protected, the data stored in them cannot be  read in programmer mode, which pr ovides a security feature (hereinafter referred to as the  anti-programmer security feature).    17.2.4  security features when the tx19a core processor is active  table 17.2.4  shows the security features available when the tx19a core processor is active.  blka  indicates block 0 (at addresses 0xbfc0_0000 to 0xbfc1_ffff),  and blkb indicates  block 1 (at addresses 0xbf c2_0000 to 0xbfc3_ffff).  in programmer mode in which a general-purpose eprom programmer is used, the security  fe atures available differ from those shown in the table below.      table 17.2.4  security features of the tx19a core processor   dsu function blka  write protect blkb write protect off on off on off on off on use of dsu yes yes yes -- -- -- -- no blka read yes yes yes -- -- -- -- yes blkb read yes yes yes -- -- -- -- yes blka program (write) yes yes no -- -- -- -- no  blkb program (write) yes no yes -- -- -- -- no blka  erase yes yes  -- -- -- -- no blkb  erase yes no yes -- -- -- -- no chip erase yes yes*1yes*1 -- -- -- -- no blk   protect yes yes yes -- -- -- -- yes blk   protect yes yes yes -- -- -- yes unprotect (all blocks) yes yes yes -- -- -- -- yes id read/protect verify yes yes yes -- -- -- -- yes yes: can be used no: cannot be used --: not supported *1:  the chip erase command erases only unprotected blocks.  enabled disabled off off on on   tmp19a71   17-6  

 tmp19a71        dsu (ejtag)-probe interface  the dsu-probe interface is used solely for software debugging using an external dsu-probe  unit. consult the dus-probe operation manual for the details on debugging using the dsu-probe.  when the tmp19a71 is in dus (ejtag) mode, the on-chip flash memory provides a security  feature.    (1)  permitting and prohibiting the use of a dsu-probe  the tmp19a71 supports on-board debugging while it is installed on a printed circuit  boar d. the tmp19a71 provides a feature to  prohibit the use of a dsu-probe to prevent  intrusive access to the flash memory. in dsu prohibit mode, a dsu-probe is denied access  to the entirety of the flash memory.   (2)  dsu prohibit mode (disabling debugging with a dsu-probe)  once program debugging is completed, write the protect command to both blocks. this  turns on the  anti-programmer security feature.  while the flash memory is in the secure  state, a dsu-probe cannot read its contents.  when the chip is powered off and powered on  again, the flash memory is put in dsu proh ibit mode, which disables debugging using a  dsu-probe until the flash memory exits dsu prohibit mode.   (3)  dsu permit mode (enabling debugging with a dsu-probe)   the flash memory can only be brought out of dsu prohibit mode by clearing the  dsuoff b it in the seqmod to 0 and then writing a special code (0x0000_00c5) to the  dsu security control (seqcnt) register. this prevents runaway software from  inadvertently turning off the dsu prohibit feature. when the flash memory exits dsu  prohibit mode, the dsu interface is enabled.  the flash memory can be secured again by  setting the dsuoff bit in the seqmod to 1 and writing 0x0000_00c5 to the seqcnt  while the chip is powered.   dsu security mode register      7 6 5  4 3 2  1  0  seqmod  bit symbol  D  D   D   D  D  D  D dsuoff  (0xffff_e510)  read/write  r r r  r r r  r  r/w    reset value  0 0 0  0 0 0  0  1    function            1: dsu disabled 0: dsu enabled     15 14 13  12 11 10  9  8   bit  sy mbol  D  D  D  D  D  D  D  D    read/write  r r r  r r r  r  r    reset value  0 0 0  0 0 0  0  0    function                  23 22 21  20 19 18  17  16   bit  sy mbol  D  D  D  D  D  D  D  D    read/write  r r r  r r r  r  r    reset value  0 0 0  0 0 0  0  0    function                  31 30 29  28 27 26  25  24   bit  sy mbol  D  D  D  D  D  D  D  D    read/write  r r r  r r r  r  r    reset value  0 0 0  0 0 0  0  0    function                note 1: the setting of the dsuoff bit takes effect after the seqcnt register is set.   note 2: this register must be accessed as a 32-bit quantity. bits 1 to 31 are read as 0.  note 3: in the flash-version device, this register is initialized by a power-on reset.    tmp19a71   17-7  note 4: this register does not support bit manipulation instructions.     

 tmp19a71          dsu security control register      7 6  5 4  3 2  1 0  seqcnt  bit symbol  D  (0xffff_e514)  read/write  w   reset  value  D    function  must be written as 0x0000_00c5.      15 14  13 12  11 10  9  8   bit  sy mbol  D   read/write  w   reset  value  D    function  must be written as 0x0000_00c5.      23 22  21 20  19 18  17 16   bit  symbol  D   read/write  w   reset  value  D    function  must be written as 0x0000_00c5.      31 30  29 28  27 26  25 24   bit  sy mbol  D   read/write  w   reset  value  D    function  must be written as 0x0000_00c5.       note 1:  this register must be accessed as a 32-bit quantity.  note 2:  this register does not support bit manipulation instructions.      (4) application example  the following flowchart shows an example of how to use the security feature with a  dsu-pr obe.                      tmp19a71  dus prohibited at power-up  (in mask rom version, dsu is prohibited by reset.) dsu permission judgment routine  (user-created)  external port  data, etc.  n  exit dus prohibit  mode?          y program seqmod and seqcnt  to exit dsu prohibit mode              [dsu prohibit mode]  the dsu-probe cannot   be used.      [dsu permit mode]  the dsu ?probe can be used until  the chip is powered off.         figure 17.2.4   using the  dsu prohibit feature    tmp19a71   17-8  

 tmp19a71        17.3  on-board programming mode  on-board programming allows re-programming of the flash memory while the tmp19a71 is  soldered on a printed circuit board. the tmp19a71 provides two types of on-programming mode.  in single boot mode, new data comes from a serial port under control of a toshiba-provided  routine in the boot rom. user boot mode allows you to create an algorithm of your own for flash  memory erase and program operations.     the tmp19a71 flash memory provides an anti -programm er security feature to prevent  intrusive access to the flash memory while in  programmer mode. this se curity feature can be  enabled upon completion of on-board programming to protect rom data from being read by third  parties.     17.3.1  user boot mode (single-chip mode)  user boot mode allows you to create a programming algorithm of your own. user boot mode  is one of the two submodes in single-chip mode; the other submode is normal mode in which  the tx19a core processor executes the user app lication. to re-program the flash memory, the  mode of operation must be switched from normal mode to user boot mode. the user  application code must include a mode judgment routine.    the user must define the conditions for mode switching, based on the logic states on i/o  ports of th e tmp19a71. additionally, the user must incorporate a programming algorithm  into the user application code. after user boot mode is entered, this programming algorithm  is copied into the on-chip ram to re-program the flash memory.    the flash memory cannot be read while it is being erased or programmed. while the flash  m emory is being erased or programmed, all interrupts including nonmaskable interrupts  must be disabled. once re-programming is co mplete, it is recommended to protect flash  memory blocks as required from accidental corruption.     the pages that follow describe the general procedures for two cases where the programming  rout ine is: a) stored within the tmp19a71 flas h memory, and b) loaded from an external  controller. for a detailed description of program and erase operations, see section 17.4  on-board programming and erasure.            tmp19a71   17-9  

 tmp19a71            user boot mode  (1-a) method 1: storing a programming routine in the flash memory     (1)  determine the conditions (e.g., pin states) required for the flash memory to enter user boot  mod e and the i/o bus to be used to transfer new program code. create hardware and software  accordingly. before installing the tmp19a71 on  a printed circuit board, write the following  program routines into a flash block using programming equipment.     (a)  mode judgment routine:  code to determine whether or not to switch to user boot mode  (b)  programming routine:  code to download ne w pr ogram code from a host controller and  re-program the flash memory   (c)  copy routine:  code t o copy the flash programming routine from the  tmp19a71 flash memory to the tmp19a71 on-chip ram    routines (a), (b) and (c) are collectively called the programming procedure.    tmp19a71  flash memory  ram [programming procedure] (a) mode judgment routine  old application   program code   host controller new application  program code  i/o (b) programming routine  (c) copy routine                                  (2)  the mode judgment routine written in one of the blocks in the flash memory determines  whet her to put the tmp19a71 flash memory in user boot mode. if the specified conditions are  met, the flash memory enters user boot mode.     tmp19a71  flash memory  ram [programming procedure] old application  program code   host controller new application  program code  i/o (a) mode judgment routine  (b) programming routine  (c) copy routine  conditions for  entering user boot  mode (defined by  the user)  0  1 rese t                                 tmp19a71   17-10 

 tmp19a71          (3)  once user boot mode is entered, execute the copy routine to copy the flash programming  routine to the tmp19a71 on-chip ram.     tmp19a71  flash memory  ram [programming procedure] (a) mode judgment routine old application   program code   host controller new application  program code  i/o (b) programming routine  (c) copy routine  (b) programming routine                                     (4)  jump program execution to the flash programming routine in the on-chip ram to erase the  flash block containing the old application program code. all interrupts including reset and  nmi must be disabled until new application pr ogram code has been written to the flash  memory.       tmp19a71  flash memory  ram [programming procedure] (a) mode judgment routine   host controller new application  program code  i/o (b) programming routine  (c) copy routine  (erased)  (b)     ` (b) programming routine                                   tmp19a71   17-11  

 tmp19a71            (5)  continue executing the flash programming routine to download new application program code  from the host controller and program it into the erased flash block. once programming is  complete, turn on the protection of that flash block.      tmp19a71  flash memory  ram [programming procedure] (a) mode judgment routine  new application  program code   host controller new application  program code  i/o (b) programming routine  (c) copy routine  (b)     ` (b) programming routine                                     (6)  drive the reset pin low to reset the tmp19a71 and enter normal mode or jump to an  arbitrary address to execute the new user application program.    tmp19a71  flash memory  ram [programming procedure] (a) mode judgment routine  new application   program code   host controller   i/o (b) programming routine  (c) copy routine  set to normal mode  0  1 rese t                                       tmp19a71   17-12 

 tmp19a71        (1-b) method 2: transferring a progra mming routine from an external host    (1)  determine the conditions (e.g., pin states) required for the flash memory to enter user boot  mode and the i/o bus to be used to transfer new program code. create hardware and software  accordingly. before installing the tmp19a71 on  a printed circuit board, write the following  program routines into a flash block using programming equipment.     (a)  mode judgment routine:  code to determine whether or not to switch to user boot mode  (b)  transfer routine:    code to download new program code from a host controller     routines (a) and (b) are collectively called the programming procedure.    also, prepare the following routine on the host controller.   (c)  programming routine:  code to re-program the flash memory    tmp19a71  flash memory  ram [programming procedure] (a) mode judgment routine  old application   program code   host controller new application  program code  i/o (b) transfer routine  (c) programming routine                                   (2)  the mode judgment routine written in one of the blocks in the flash memory determines  whether to put the tmp19a71 flash memory in user boot mode. if the specified conditions are  met, the flash memory enters user boot mode.     tmp19a71  host controller i/o (c) programming routine new application  program code  0   1 reset conditions for  entering user bo ot  mode (defined by  the user)  ram flash memory  old application  program code   [programming procedure] (b) transfer routine  (a) mode judgment routine                                  tmp19a71   17-13  

 tmp19a71            (3)  once user boot mode is entered, execut e the transfer routine to download the flash  programming routine from the host controller to the tmp19a71 on-chip ram.     tmp19a71  flash memory  ram [programming procedure] (a) mode judgment routine old application  program code   host controller new application   program code  i/o (b) transfer routine  (c) programming routine (c) programming routine                                     (4)  jump program execution to the flash programming routine in the on-chip ram to erase a flash  block containing the old application program code. all interrupts including reset and nmi  must be disabled until new application program code has been written to the flash memory.     tmp19a71  flash memory  ram [programming procedure] (a) mode judgment routine   host controller new application   program code  i/o (b) transfer routine  (erased)  (c)  programming routine (c) programming routine                                  tmp19a71   17-14 

 tmp19a71          (5)  continue executing the flash programming  routine to download new application program  code and program it into the erased flash bloc k. once programming is complete, turn on the  protection on that flash block.     tmp19a71  flash memory ram [programming procedure] (a) mode judgment routine new application  program code   host controller new application  program code  i/o (b) transfer routine  (c) programming routine (c) programming routine                                     (6)  driv e the reset pin low to reset the tmp19a71 and enter normal mode or jump to an  arbitrary address to execute the new user application program.        tmp19a71  host controller i/o     0   1 reset  set to normal mode  ram flash memory new application   program code   [programming procedure] (b) transfer routine  (a) mode judgment routine                                     tmp19a71   17-15  

 tmp19a71          17.3.2 single boot mode  in single boot mode, the flash memory can be  re-programmed by using a program contained  in the tmp19a71 on-chip boot rom. this boot rom is a masked rom. when single boot  mode is selected upon reset, the boot rom is mapped to the address region including the  interrupt vector table while the flash memory is mapped to an address region different from it  (see  figure 17.2.2 ).    single boot mode allows for serial programming of the flash memory. the sio (sio2) of the  tmp19a71 is connect ed to an external host controller. via this serial link, a programming  routine is downloaded from the host controller to the tmp19a71 on-chip ram. then, the  flash memory is re-programmed by executing the programming routine. the host sends out  both commands and programming data to re-program the flash memory.     communications between the sio2 and the host must follow the prescribed protocol  described later . to secure the contents of  the flash memory, password verification is  performed before a programming routine is downloaded into the on-chip ram. if password  verification fails, the transfer of a programming routine itself is aborted. all interrupts  including nonmaskable interrupts must be disabled while the boot program is executed.    once re-programming is comple te , it is recommended to protect flash memory blocks as  required from accidental corruption during su bsequent operation in single-chip (normal)  mode. for a detailed description of erase and program operations, see section 17.4 on-board  programming and erasure.           tmp19a71   17-16 

 tmp19a71          single boot mode  (2-a) general procedure: using a programming algorithm in the on-chip boot rom    (1)  the flash block containing the older version of the program code need not be erased before  executing the programming routine. since a programming routine and programming data are  transferred via the uart2 or sio2, the uart 2 or sio2 pins must be connected to a host  controller.  prepare a programming routine on the host controller. (the sio2 is used here.)    tmp19a71  flash memory  ram     old application  program c ode  (or erased state)   host controller new application   program code  i/o (a) programming routine boot rom  sio2                                   (2)  reset the tmp19a71 with the mode setting pins held at appropriate logic values for  re-booting from the on-chip boot rom. in single boot mode, the 12-byte password transferred  from the host controller is fi rst compared to the password stored in the user application  program in the flash memory. (if the flash memory has already been erased, password  verification is performed using the erased data.)    tmp19a71  host controller i/o 0   1 reset (a) programming routine sio2 boot rom    old application  program code  (or erased state)     ram flash memory  new application   program c ode                                  tmp19a71   17-17  

 tmp19a71            (3)  if password verification is  successful, the boot program loads the programming routine from  the host controller into the on-chip ram.  the programming routine must be stored in the  address range of 0xffff_9800 to 0xffff_afff.     tmp19a71  flash memory  ram     old application  program c ode   (or erased state)   host controller new application   program code  i/o (a) programming routine boot rom  sio2 (a) programming routine                                      (4)  the tx19a core processor jumps to the programming routine in the on-chip ram to erase the  flash block containing the old application program code. (the block erase or chip erase  command may be used.)    tmp19a71  flash memory  ram   host controller new application   program code  i/o erased  (a)  programming routine sio2 boot rom  (a) programming routine                                  tmp19a71   17-18 

 tmp19a71          (5)   next, the programming routine loads new application program code from the host controller  into the erased flash block. once programming is complete, the flash block is placed under  protection.  in the example below, new program code comes from the same host controller via the same sio  chann el as for the programming routine. howeve r, once the programming routine has begun to  execute, the transfer path and the source of the transfer can be changed as desired. create  board hardware and a programming routine to suit your particular needs.     note:  the boot rom provides no vector area for all maskable interrupts and nmi. while the programming routine is  executed, no exception should be allowed to occur.        tmp19a71  flash memory  ram     new application  program c ode   host controller new application  program code  i/o (a) programming routine sio2 boot rom  (a) programming routine                                    (6)  when the flash memory has been programmed,  power off the board and disconnect the cable  connecting the host controller.  then, turn on the power again and re-boot the tmp19a71 in  single-chip mode (normal mode) to execute the new application program.       tmp19a71  host controller   0   1 reset set to single-chip  mode (no rmal mode)  sio2 boot rom  ram     new application  program c ode   flash memory                                      tmp19a71   17-19  

 tmp19a71          (1)  connection examples in single boot mode  in single boot mode, serial transfer is used to re-program the flash memory while the  tmp19 a71 is installed on a printed circuit board.  in this mode, the sio (channel 2) of the  tmp19a71 is connected to a host  controller (programming tool).  the host controller issues  commands to the target board to perform programming operations.  figure 17.3.1  and figure  17.3.2  show examples of host-to-target connection.       target board  tx2 (p86)  rx2 (p85)  dvcc2  vcc pc  rs232c      rom    mode  control  vcc vcc  reg.  a c  100v  host controller  dvss  reset tmode     mcu          mode  control  rx vss  tx reset        boot  mode  selection  logic  boot       ram  reg. nmi  tmp19a71                                                           figure 17.3.1   exam ple of connection between a host controller  and a target board in single boot mode   (when the sio2 is configured for uart mode)      tmp19a71   17-20 

 tmp19a71            target board  tx2 (p86)  rx2 (p85)  dvcc2  vcc pc  rs232c      rom    mode  control  vcc vcc  reg.  a c  100v  host controller  dvss  reset tmode     mcu          mode  control  rx vss  tx reset     boot       ram  reg. nmi    p80  tbus y sclk2 (p87)  tck       boot  mode  selection  logic  tmp19a71                                                               figure 17.3.2   exam ple of connection between a host controll er and a target board in single boot mode  (when the sio2 is configured for i/o interface mode)                                 tmp19a71   17-21  

 tmp19a71             ( 2)  configuring for single boot mode  to perform on-board programming, boot up the tmp19a71 in single boot mode, as  shown below .   test0 = 0  boot = 0  reset = 0    1  while the reset pin is held at logic 0,  set the test0 and bo ot (p94) pins at the  logic values shown above. then, driving the reset pin high boots up the tmp19a71 in  single boot mode.     (3) memory map  figure 17.3.3  shows a comparison of the memory maps in single-chip (normal) mode and  si ngle boot mode. in single boot mode, the on-chip flash memory is mapped to physical  addresses 0x4000_0000 through 0x400f_ffff and virtual addresses 0x0000_0000 through  0x000f_ffff. the on-chip boot rom (mask rom) is mapped to physical addresses  0x1fc0_0000 through 0x1fc0_1fff.   normal mode  single boot mode    0x1fc0_1fff  0x1fc0_0000  0x0000_0000  0xffff_ffff   0xffff_bfff 0xffff_9800 0xff3f_ffff 0xff20_0000 0xc000_0000 0x400f_ffff 0x4000_0000 0x1fc3_ffff 0x1fc0_0400 0x1fc0_0000 0x2000_0000 0xff00_0000 0xbf00_0000 0xffff_ffff   0xffff_bfff 0xffff_9800 0xff3f_ffff 0xff20_0000 0xc000_0000 0x4003_ffff 0x4000_0000 0x2000_0000 0xff00_0000 0xbf00_0000 on-chip  peripherals  0x0000_0000 on-chip ram (10kb)  (reserved)  used for debugging  (reserved)  (reserved)    (reserved)    on-chip rom  shadow  inaccessible   (512 mb)    user program   area  maskable interrupt  area  exception vector  area    internal  rom    (reserved)      boot mrom  (6 kb)    inaccesible   (512 mb)  on-chip   flash rom  (reserved)  used for debugging  (reserved)  (reserved)  on-chip ram (10kb)  on-chip  peripherals                                                                note: the addresses shown above are physical addresses.     figure 17.3.3   memory maps for normal and single boot modes    tmp19a71   17-22 

 tmp19a71        (4) interface specifications  in single boot mode, an sio channel is  used for communications with a programming  controller. both uart (asynchronous) and i/ o interface (synchronous) modes are supported.  to perform on-board programming, the interface specifications shown below must also be set  on the controller side.   uart mode  com munications channel  : uart2  transfer mode  : uart (asynchronous) mode, full-duplex  data length  : 8 bits  parity bit  : none  stop bit  : 1 bit  baud rate  : up to 437.5 kbps (at 56 hz)                                                up to 312.5 kbps (at 40 hz)  others  : lsb first, sc2mod2.wbuf=0   ?   ?     i/o interface mode  commun ications channel  : sio2  transfer mode  : i/o interface mode, half-duplex  synchronization signal (sclk2)   sclk input mode (sc2cr = 0x01)  handshaking signal  : p80 configured as an output  baud rate  : up to 3 mbps (at 56 hz)                                                 up to  2.5 mbps (at 40 mhz)  others  : lsb first, sc2mod2.wbuf = 0      table 17.3.1   re quired pin connections  interface  pin  uart mode  i/o interface mode  dvcc3 required  required  power supply pins  dvss required  required  mode setting pin  boot   required required  reset pin  reset   required required  tx2 required  required  rx2 required  required  sclk2  not required  required (input mode)  communications pins  p80  not required  required (output mode)      (5)  data transfer format  table 17.3.2 lists the commands to  be issued fr om the host controller to the target board in  single boot mode. tables 17.3.3 to 17.3.5 illustrate the sequence of two-way communications  that should occur in response to each command.     table 17.3.2   si ngle boot mode commands  code command  0x10 ram  transfe r  0x20  show flash memory sum  0x30  show product information      tmp19a71   17-23  

 tmp19a71          table 17.3.3   transfer format for the ram transfer command    byte  data transferred from the controller   to the  tmp19a71  baud rate  data transferred from the tmp19a71  to the cont roller   boot rom  1st byte  serial operation mode and baud rate  for uart mode  0x86  for i/o interface mode (note 2)  0x30  specified  baud rate  (note 1)  ?    2nd  b yte  ?     ack for the serial operation mode byte    for uart mode      normal acknowledge  0x86  (the boot program aborts if the baud rate  cannot be set cor rectly.)   for i/o interface mode      normal acknowledge  0x30    3rd byte  command code  (0x10 )    ?    4th  b yte  ?     ack for the command code byte (note 3)    normal acknowledge   0x30    negative acknowledge  0x11    communication error  0x18    5th byte   to   16th b yte  password sequence (12 bytes)    (0x0000_0474 to 0x0000_047f)    ?     17th byte  checksum value for  5th to 16th bytes ( note 4)   ?    18th  b yte  ?     ack for the checksum byte (note 3)    normal acknowledge  0x10    negative acknowledge  0x11    communication error  0x18    19th byte  ram storage start address 31 to 24 (note 5)   ?     20th byte  ram storage start address 23 to 16 (note 5)   ?     21st byte  ram storage start address 15 to 8  (note 5)    ?     22nd byte  ram storage start address 7 to 0 (note 5)    ?     23rd byte  ram storage byte count 15 to 8 (note 5)    ?     24th byte  ram storage byte count 7 to 0 (note 5)    ?     25th byte  checksum value for  19th to 24th  bytes (note 4)   ?    26th  b yte  ?     ack for the checksum byte (note 3)    normal acknowledge  0x10    negative acknowledge  0x11    communication error  0x18   27th  b yte  to  mth byte  ram storage data    ?    (m  +  1)th byte  checksum value for 27th to mth bytes (note 4)   ?    (m  +  2)th byte  ?     ack for the checksum byte (note 3)    normal acknowledge  0x10    negative acknowledge  0x11    communication error  0x18  ram (m  +  3)th byte  ?     jump to ram storage start address    note 1:  in i/o interface mode, the baud rate for transferring the 1st and 2nd bytes must be 1/16 of the specified baud rate.   note 2:  in i/o interface mode, a waveform that allows the serial operation mode to be determined should be generated.   note 3:  in case of any negative acknowledgment, the boot program returns to a state in which it waits for a command code (3rd  b yte). in i/o interface mode, no acknowledgment is returned for a communicaion error.   note 4:  the checksum value is obtained by adding all the bytes of transmitted data together, dropping the carries, and taking t he   two?s complement of the total sum.    note 5:  the 19th to 24th bytes must be within the ram address range 0xffff_9800 to 0xffff_afff.      tmp19a71   17-24 

 tmp19a71        table 17.3.4   transfer format for the show flash memory sum command    byte  data transferred from the controller  to the tmp19a71  baud rate data transferred from the tmp19a71   to the cont roller   boot rom  1st byte  serial operation mode and baud rate  for uart mode  0x86  for i/o interface mode (note 2)  0x30  specified  baud rate  (note 1)  ?    2nd  b yte  ?     ack for the serial operation mode byte     for uart mode     normal acknowledge  0x86         (the boot program aborts if the baud rate cannot be set cor rectly.)  for i/o interface mode      normal acknowledge  0x30    3rd byte  command code  (0x20 )    ?    4th  b yte  ?     ack for the command code byte (note 3)    normal acknowledge  0x20    negative acknowledge  0x21    communication error  0x28   5th  b yte  ?     sum (upper byte)   6th  b yte  ?     sum (lower byte)   7th  b yte  ?     checksum value for 5th and 6th bytes (note 4)   8th byte  (wait for the next command code.)    ?     note 1:  in i/o interface mode, the baud rate for transferring the 1st and 2nd bytes must be 1/16 of the specified baud rate.   note 2:  in i/o interface mode, a waveform that allows the serial operation mode to be determined should be generated.   note 3:  in case of any negative acknowledgment, the boot program returns to a state in which it waits for a command code (3rd  b yte).  in i/o interface mode, no acknowledgment is returned for a communication error.   note 4:  the checksum value is obtained by adding all the bytes of transmitted data together, dropping the carries, and taking t he   two?s complement of the total sum.   note 5:  the sum value is the lower 16 bits of a value obtained by adding all the bytes in the flash memory together.   sum (high) = sum[ 15 : 8 ], sum (low) = sum[ 7 : 0 ]    tmp19a71   17-25  

 tmp19a71          table  17.3.5   transfer format for the show product information command (1/2)    byte  data transferred from the controller   to the  tmp19a71  baud rate data transferred from the tmp19a71   to the cont roller   boot rom  1st byte  serial operation mode and baud rate  for uart mode  0x86 for i/o interface mode (note 2)  0x30 specified  baud rate   (note 1 )  ?    2nd  b yte  ?     ack for the serial operation mode byte     for uart mode     normal acknowledge   0x86         (the boot program aborts if the baud rate   cannot be set correctl y.)    for i/o interface mode      normal acknowledge  0x30    3rd byte  command code  (0x30 )   ?    4th  b yte  ?     ack for the command code byte (note 3)    normal acknowledge  0x30    negative acknowledge  0x31    communication error  0x38   5th  b yte  ?     flash memory data (at address 0x0000_0470)   6th  b yte  ?     flash memory data (at address 0x0000_0471)   7th  b yte  ?     flash memory data (at address 0x0000_0472)   8th  b yte  ?     flash memory data (at address 0x0000_0473)   9th  b yte  to   20th byte  ?     product name (12-byte ascii code)   ?tx19a71fy? + 0x20, 0x20, 0x20 from the 9th byte  21st  b yte  to   24th byte  ?     password comparison start address (4 bytes)  0x74, 0x04, 0x00, 0x00 from the 21st byte   25th  b yte  to   28th byte  ?     ram start address (4 bytes)   0x00,0x98, 0xff, 0xff from the 25th byte   29th  b yte  to  32nd byte  ?     dummy data (4 bytes)  0xff, 0xa7, 0xff, 0xff from the 29th byte   33rd  b yte  to  36th byte  ?     ram end address (4 bytes)   0xff, 0xbf, 0xff, 0xff from the 33rd byte   37th  b yte  to  40th byte  ?     dummy data (4 bytes)  0x00, 0xa8, 0xff, 0xff from the 37th byte   41st  b yte  to  44th byte  ?     dummy data (4 bytes)  0xff, 0xaf, 0xff, 0xff from the 41st byte   45th  b yte  to  46th byte  ?     fuse information (2 bytes)  0x00, 0x00 from the 45th byte   47th  b yte  to  50th byte  ?     flash memory start address (4 bytes)  0x00, 0x00, 0x00, 0x00 from the 47th byte   51st  b yte  to  54th byte  ?     flash memory end address (4 bytes)  0xff, 0xff, 0x03, 0x00 from the 51st byte   55th  b yte  to  56th byte  ?     flash memory block count (2 bytes)  0x02, 0x00 from the 55th byte   57th  b yte  to  60th byte  ?     start address of a group of the same-size flash  blocks  ( 4 bytes)  0x00, 0x00, 0x00, 0x00 from the 57th byte      tmp19a71   17-26 

 tmp19a71        table 17.3.5   transfer format for the show device information command (2/2)    byte  data transferred from the controller  to the  tmp19a71  baud rate data transferred from the tmp19a71   to the cont roller  root rom  61st byte  to  64th byte  ?     size (in half words) of the same-size flash blocks  (4 b ytes)  0x00, 0x00, 0x01, 0x00 from the 61st byte   65th  b yte  ?     number of flash blocks of the same size (1 byte)  0x02   66th  b yte  ?     checksum value for the 5th to 65th bytes (note 4)   67th byte  (wait for the next command code.)    ?     note 1:  in i/o interface mode, the baud rate for transferring the 1st and 2nd bytes must be 1/16 of the specified baud rate.  note 2:  in i/o interface mode, a waveform that allows the serial operation mode to be determined should be generated.  note 3:  in case of any negative acknowledgment, the boot program returns to a state in which it waits for a command code (3rd  b yte). in i/o interface mode, no acknowledgment is returned for a communication error.   note 4:  the checksum value is obtained by adding all the bytes of transmitted data together, dropping the carries, and taking t he  t wo?s complement of the total sum.       tmp19a71   17-27  

 tmp19a71          (6)   overview of the boot program commands  when single boot mode is selected, the boot program is automatically executed on startup.  t he boot program offers the following three commands (each command is explained in detail  in the subsections that follow):     1.   r am transfer command  the ram transfer command stores program code transferred from a host controller to the  on-chip ram and executes the program once the transfer is successfully completed. the  maximum program size is 6 kb ytes (0xffff_9800 to 0xffff_afff).    the ram transfer command enables the user to control on-board programming of the  flash memory in a unique manner by providing the means for downloading a user-created  programming routine. the programming rout ine must use the flash memory command  sequences described in section 17.4 on -board programming and erasure.     before initiating a transfer, the ram transfer command checks a password sequence  coming from the controller against the password stored in the flash memory. if they do not  match, the ram transfer command aborts.     2.   sho w flash memory sum command  the show flash memory sum command adds the contents of the flash memory and  returns the lower 16 bits of the result. the boot program does not provide a command to  read out the contents of the flash memory. instead, the show flash memory sum  command can be used for soft ware revision management.    3.  show product information command  t he show product information command provides product information, such as the  product name and on-chip memory configurat ion, stored at addresses 0x0000_0470 to  0x0000_0473 in the flash memory.  in addition to the show flash memory sum command,  this command can be used for so ftware revision management.         tmp19a71   17-28 

 tmp19a71        1)  ram transfer command (see  table 17.3.3 )    1.  the 1st byte specifies which one of the two serial operation modes is used. for a  de tailed description of how the serial operation mode is determined, see subsection 5)  determination of a serial operation mode. if it is determined as uart mode, the boot  program then checks if the sio2 is programmable to the baud rate at which the 1st  byte was transferred. the 1st byte is transferred with receive operation disabled  (sc2mod.rxe = 0).     ?   t o communicate in uart mode  the controller sends 86h to the target bo ard in uart data format at the desired  baud rate. if the serial operation mode is determined as uart, then the boot  program checks if the sio2 can be programmed to the baud rate at which the 1st  byte was received. the time (number of instruction execution cycles) required for  this operation varies with the operating frequency and baud rate used. if the  desired baud rate cannot be used, the boot program aborts, disabling any  subsequent communication. in this case,  a reset is required. if necessary, the  controller should set a time limit for transferring the 2nd byte as appropriate to  the baud rate used.     ?   t o communicate in i/o interface mode  the controller sends the 1st byte to the ta rget board to gen erate a waveform that  allows the serial operation mode to be determined as i/o interface mode. (for  details, see subsection 5) determination of a serial operation mode.)  when the  boot program determines that communicati ons can be performed in i/o interface  mode at the desired baud rate, the handshak e pin is driven high. if the high level  is not detected on the handshake pin within the expected time period, this  indicates that the boot program has aborted after determining that the sio2 is  not programmable to the desired baud rate.  in this case, a reset is required. the  command sequence must be started again from the 1st byte at another baud rate.   in i/o interface mode, the tx19a core processor sees the serial receive pin as if it  wer e a general-purpose input port and monitors its logic transitions. if the baud  rate of incoming data is high or the chip?s operating frequency is high, the tx19a  core processor may not be able to keep up with the speed of logic transitions. to  prevent such situations, the 1st and 2nd bytes must be transferred at 1/16 of the  desired baud rate; then the boot program calculates 16 times that as the desired  baud rate. at this time, the transmission of one byte should be completed before  an overflow occurs in the tmrb0 (see figure 17.3.6).  when the serial operation mode is determ ined as i/o interface mode, the sio2 is  configured for sclk in put mode. beginn ing with the 3rd byte, the controller  must ensure that the ac timing restrict ions are satisfied at the selected baud  rate. in i/o interface mode, the boot pr ogram does not check the receive error  flag; thus there is no such thing as error acknowledge (bit 3) (18h).    2.  the 2nd byte, transmitted from the target  b oard to the controller, is an acknowledge  response to the 1st byte. the boot program echoes back the first byte: 86h for uart  mode and 30h for i/o interface mode.     ?   uart mode  if the sio2  can be programmed to the baud rate at which the 1st byte was    tmp19a71   17-29  

 tmp19a71          transferred, the boot program programs the br2cr and br2add registers and  sends back 86h to the controller as an acknowledge. if the sio2 is not  programmable at that baud rate, the boot  program simply aborts with no error  indication. following the 1st byte, the controller should allow for a time-out  period. if it does not receive 86h within the allotted time-out period, the  controller should give up the communication. the boot program sets the rxe bit  in the sc2mod to 1 to enable reception be fore loading the transmit buffer with  86h.     ?   i/o inter face mode  the boot program programs the sc2mod and sc2cr registers to configure the  sio2 in i/o interface mode and writes 30h to the sc2buf. then, the sio2 waits  for the sclk2 signal to come from the controller. following the transmission of  the 1st byte, the controller must wait for the rising edge of the handshaking pin  before sending the sclk clock. this must be done at 1/16 of the desired baud rate.  if the controller receives 30h as the 2nd byte, this should be taken as the  go-ahead. the controller must then delive r the 3rd byte to the target board at a  rate equal to the desired baud rate. the boot program sets the sc2mod.rxe bit  to 1 before 30h is written to the transm it buffer. in i/o interface mode, receive  errors are not checked.      3.  the 3rd byte, which the target board receives from the controller, is a command. the  code for the  ram transfer command is 10h.     4.  the 4th byte, transmitted from the target  board t o the controller, is an acknowledge  response to the 3rd byte. before sending back the acknowledge response, the boot  program checks for a receive error. if there was a receive error, the boot program  transmits x8h and returns to the state in which it waits for a command again. in this  case, the upper four bits of the acknowledge response are undefined?they hold the  same values as the upper four bits of the preceding command.     if the 3rd byte is equa l to an y of the command codes listed in  table 17.3.2 , the boot  pro gram echoes it back to the controller. when the ram transfer command was  received, the boot program echoes back a value of 10h and then branches to the ram  transfer routine. once this branch is taken, a password check is done. password  checking is detailed later in this subsection. if the 3rd byte is not a valid command,  the boot program sends back 11h to the co ntroller to indicate a command error and  returns to the state in which it waits for a command.  in this case, the upper four bits  of the response are undefined?they hold the same values as the upper four bits of  the preceding command.     5.  the 5th to 16th bytes, which the target board receives from the controller, are a  1 2-byte password. the 5th byte is compared to the contents of address 0x0000_0474  in the flash memory; the 6th byte is compared to the contents of address  0x0000_0475 in the flash memory; likewi se, the 16th byte is compared to the  contents of address 0x0000_047f in the flash memory.     6.  the 17th byte is a checksum value for the password sequence (5th to 16th bytes). to  calcu late the checksum value for the 12-byte password, add the 12 bytes together,  drop the carries and take the two?s complement of the total sum. transmit this    tmp19a71   17-30 

 tmp19a71        checksum value from the controller to the  target board. the checksum calculation is  described in detail later in this section.     7.   the 18 th byte, transmitted from the target board to the controller, is an acknowledge  response to the 5th to 17th bytes. first, the ram transfer routine checks for a  receive error in the 5th to 17th bytes. if there was a receive error, the boot program  sends back 18h and returns to the state in  which it waits for a command (i.e., 3rd  byte) again. in this case, the upper four bits of the acknowledge response are the  same as those of the preceding command (i.e., all 1s).     next, the ram transfer routine performs the checksum operation to ensure data  integrity. adding the 5th to 17th bytes together must result in zero (with the carries  dropped). if it is not zero, the ram transfer routine sends back 11h to the controller  to indicate a checksum error and returns to the state in which it waits for a command  (i.e., the 3rd byte) again.    finally, the ram transfer routine examines the result of the password check. if a  password error is determined, the ram transfer routine sends back 11h to the  controller and returns to the state in which it waits for a command (i.e., the 3rd byte)  again.      for data sequences that can be used as a password, see subsection 6) password.    when all the above checks have been successful, the ram transfer routine returns a  norm al acknowledge response (10h) to the controller.     8.  the 19th to 22nd bytes, which the target board receives from the controller, indicate  the start ad dress of the ram region where subsequent data should be stored. the  19th byte corresponds to bits 31 to 24 of the address, and the 22nd byte corresponds  to bits 7 to 0 of the address.     9.  the 23rd and 24th bytes, which the target board receives from the controller,  ind icate the number of bytes that will be transferred from the controller to be stored  in the ram. the 23rd byte corresponds to bits 15 to 8 of the transfer byte count, and  the 24th byte corresponds to bits 7 to 0 of the transfer byte count.     10. the 25th byte is a checksum value for the 19th to 24th bytes. to calculate the  checksum  value, add all these bytes together, drop the carries and take the two?s  complement of the total sum. transmit this checksum value from the controller to  the target board. the checksum calculatio n is described later in this section.     11.   the 26th byte, transmitted fr om the targ et board from the controller, is an  acknowledge response to the 19th to 25th bytes. first, the ram transfer routine  checks for a receive error in the 19th to 25t h bytes. if there was a receive error, the  ram transfer routine sends back 18h and retu rns to the state in which it waits for a  command (i.e., the 3rd byte). in this case , the upper four bits of the acknowledge  response are the same as those of the preceding command (i.e., all 1s).     next, the ram transfer routine performs the checksum operation to ensure data  integrity.  adding the 19th to 25th bytes together must result in zero (with the    tmp19a71   17-31  

 tmp19a71          carries dropped).  if it is not zero, the  ram transfer routine sends back 11h to the  controller to indicate a checksum error and  returns to the state in which it waits for a  command (i.e., the 3rd byte).     ?   the ram storage addresses must be  within the range of 0xffff_9800 to  0xffff_afff. although the boot program does not perform address checks,  ram transfer may not be performed properly if other ram address locations are  specified as they are used in the program.     whe n the above checks have been successful, the ram transfer routine returns a  normal acknowledge response (10h) to the controller.      12.  the 27th to m?th bytes from the controller are stored in the on-chip ram of the  tmp19 a71. storage begins at the address specified by the 19th to 22nd bytes and  continues for the number of bytes specified by the 23rd and 24th bytes.      13. the (m  +  1) th byte is a checksum value. to calculate the checksum value, add the  27th to m?th bytes together, drop the carri es and take the two?s complement of the  total sum. transmit this checksum value from the controller to the target board. the  checksum calculation is described in detail later in this section.     14. the (m  +  2 )th byte is an acknowledge response to the 27th to (m+1)th bytes. first,  the ram transfer routine checks for a receiv e error in the 27th to (m+1)th bytes. if  there was a receive error, the ram transfer routine sends back 18h and returns to  the state in which it waits for a command (i.e., the 3rd byte) again. in this case, the  upper four bits of the acknowledge response are the same as those of the preceding  command (i.e., all 1s).   next, the ram transfer routine performs the checksum operation to ensure data  integrity. adding the 27th to (m+1)th bytes together must result in zero (with  carries dropped). if it is not zero, the  ram transfer routine sends back 11h to the  controller to indicate a checksum error and returns to the state in which it waits for  a command (i.e., the 3rd byte) again. if all the above checks are successful, the ram  transfer routine returns a normal acknowledge response (10h) to the controller.     15.  if the (m  +  2)th byt e was a normal acknowledge  response, a branch is made to the  address specified by the 19th to 22nd bytes in 32-bit isa mode.     tmp19a71   17-32 

 tmp19a71        2)  show flash memory sum command (see  table 17.3.4 )    1.  the processing of the 1st and 2nd bytes are the same as for the ram transfer  co mmand.     2.  the 3rd byte, which the target board receives from the controller, is a command. the  code for the  show flash me mory sum command is 20h.     3.  the 4th byte, transmitted from the target  board t o the controller, is an acknowledge  response to the 3rd byte. the processing of the 4th byte is the same as for the ram  transfer command except that the command code is 20h.     4.  the show flash memory sum routine adds all the bytes of the flash memory  togeth er. the 5th to 6th bytes, transmitted  from the target board to the controller,  indicate the upper and lower bytes of  this total sum, respectively. the sum  calculation is described in detail later in this section.     5.  the 7th byte is a checksum value for the 5th and 6th bytes. to calculate the  checksum va lue, add the 5th and 6th bytes together, drop the carry and take the  two?s complement of the sum. transmit this checksum value from the controller to  the target board.     6.  the 8th byte is the next command code.     tmp19a71   17-33  

 tmp19a71          3)  show product information command (see  table 17.3.5 )    1.  the processing of the 1st and 2nd bytes are the same as for the ram transfer  co mmand.     2.  the 3rd byte, which the target board receives from the controller, is a command. the  code for the  show product in formation command is 30h.     3.  the 4th byte, transmitted from the target  board t o the controller, is an acknowledge  response to the 3rd byte. the processing of the 4th byte is the same as for the ram  transfer command except that the command data is 30h.     4.  the 5th to 8th bytes, transmitted from the target board to the controller, are the data  read  from addresses 0x0000_0470 to 0x0000_0473 in the flash memory. software  revision management is  possible by storing software in formation such as an id in  these locations.    5.  the 9th to 20th bytes, transmitted from  th e target board to the controller, indicate  the product name, which is ?tx19a71fy? in  ascii code followed by 20h, 20h, and  20h (12 bytes).     6.  the 21st to 24th bytes, transmitted from  the target board to th e controller, indicate  the start address of the flash memory area  containing the password (74h, 04h, 00h ,  00h ).     7.  the 25th to 28th bytes, transmitted from the target board to the controller, indicate  the start a ddress of the on-chip ram (00h, 98h, ffh, ffh).     8.  the 29th to 32nd bytes, transmitted from  the tar get board to the controller, are  dummy data (ffh, a7h, ffh, ffh).     9.  the 33rd to 36th bytes, transmitted from th e targ et board to the controller, indicate  the end address of the on-chip ram (ffh, ffh, bfh, ffh).     10.   the 3 7th to 40th bytes, transmitted from the target board to the controller, are 00h,  a8, ffh and ffh.  the 41st to 44th bytes, transmitted from th e target board to the controller, are ffh,  afh, ffh and ffh.     11.  the 45th and 46th bytes, transmitted from the target board to the controller, indicate  whet her the security and protect bits are available and whether the flash memory is  divided into blocks.  bit 0 indicates the presen ce or absence of the security bit; it is 0  if the security bit is available.  bit 1 indicates the presence or absence of the protect  bits; it is 0 if the protect bits are available.  if bit 2 is 0, it indicates that the flash  memory is divided into blocks. the remaining bits are undefined. the 45th and 46th  bytes are 00h, 00h.     12.  the 47th to 50th bytes, transmitted from the target board to the controller, indicate  the start a ddress of the on-chip flash memory (00h, 00h, 00h, 00h).     tmp19a71   17-34 

 tmp19a71          13.  the 51st to 54th bytes, transmitted from  the target board to the controller, indicate  the end address of the on-chip fl ash memory (ffh, ffh, 03h, 00h).     14.  the 55th and 56th bytes, transmitted from the target board to the controller, indicate  the numb er of flash blocks available (02h, 00h).     15.  the 57th to 92nd bytes, transmitted from the target board to the controller, contain  informat ion about the flash blocks. flash bl ocks of the same size are treated as a  group. information about the flash blocks in dicate the start address of a group, the  size of the blocks in that group (in half words) and the number of the blocks in that  group.      the 57th t o 65th bytes are the information about 128-kbyte blocks (block 0 and  block 1). see  table 17.3.5  for the values of bytes transmitted.     16.  the 66th byte, transmitted from the target  b oard to the controller, is a checksum  value for the 5th to 65th bytes. the checksum value is calculated by adding all these  bytes together, dropping the carries and taking the two?s complement of the total  sum.     17.  the 67th byte is the next command code.     tmp19a71   17-35  

 tmp19a71          4) acknowledge responses    the boot program returns to the controller specific codes to notify processing states.  table  17.3.6  to  table 17.3.8  show the values of possible acknowledge responses to the received data.  t he upper four bits of the acknowledge response are equal to those of the command being  executed. bit 3 of the code indicates a receive error. bit 0 indicates an invalid command error,  a checksum error or a password error. bit 1 and bit 2 are always 0. receive error checking is  not performed in i/o interface mode.      table 17.3.6   a ck response to the serial operation mode bytes  return value  meaning  0x86  the sio can be configured to operate in uart mode. (note)  0x30  the sio can be configured to operate in i/o interface mode.   note:   if the serial operation mode is determined as uart, the boot program checks if the sio can be  programmed to the baud rate at which the operation mode byte was transferred. if the baud rate  is not possible, the boot program aborts without sendig back any response.     table 17.3.7   a ck response to the command byte  return value  meaning  0xn8  (note)  a receive error occurred while a command code was being received.   0xn1  (note)  an undefined command code was received. (reception was completed normally.)  0x10  the ram transfer command was received.  0x20  the show flash memory sum command was received.  0x30  the show product information command was received.   note:  the four high-order bits of the ack response are the same as those of the preceding command  code.     table 17.3.8   a ck response to the checksum byte  return value  meaning  0xn8 (note)  a receive error occurred.  0xn1 (note)  a checksum or password error occurred.   0xn0 (note)  the checksum was correct.   note:  the four high-order bits of the ack response  are the four high-order bits of the preceding  command code. they are 1 if a password error occurred.         tmp19a71   17-36 

 tmp19a71        5)  determination of a serial operation mode    the first byte from the controller determines the serial operation mode. to use uart mode  for com munications between the controller and the target board, the controller must first  send a value of 86h at a desired baud rate to the target board. to use i/o interface mode, the  controller must send the first byte with a wave form satisfying tab > tc d (30h is sent here)  at 1/16 of the desired baud rate.   figure 17.3.4  shows the waveforms for the first byte.       bit 7   bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6   start stop   point a   point d     point b point c                         figure 17.3.4   s erial operation mode byte    after the reset state is released, the boot prog ram  monitors the first serial byte from the  controller with the sio reception disabled, and calculates the intervals of tab, tac and tad   shown in  figure 17.3.4 .   figure 17.3.5  shows a flowchart describing  th e steps to determine the  intervals of tab, tac and tad. as shown in th e flowchart, the boot program captures timer  counts each time a logic transition occurs in th e first serial byte. consequently, the calculated  tab, tac and tad intervals are bound to have slight  errors. if the transfer goes at a high baud  rate, the tx19a core processor might not be able  to keep up with the speed of logic transitions  at the serial receive pin. in particular, i/o interface mode is more prone to this problem since  its baud rate is generally much higher than th at for uart mode. to avoid such a situation,  the controller should send the first serial  byte at 1/16 of the desired baud rate.     the flowchart in  figure 17.3.6  shows how the boot program distinguishes between uart  and i/o interfac e modes. if the length of tab is  equal to or less than the length of tcd, the  serial operation mode is determined as uart mode. if the length of tab is greater than tcd,  the serial operation mode is determined as i/o interface mode. bear in mind that if the baud  rate is too high or the timer operating frequency is too low, the timer resolution will be coarse,  relative to the intervals between logic transiti ons. this becomes a problem due to inherent  errors caused by the way in which timer counts  are captured by software; consequently the  boot program might not be able to determine the serial operation mode correctly. (serial  operation mode settings must be made again in the programming routine.)  for example, the serial operation mode may be determined to be i/o interface mode when  the int ended mode is uart mode. to avoid such a situation, when uart mode is utilized, the  controller should allow for a time-out period wi thin which it expects to receive an echo-back  (86h) from the target board. the controller should give up the communication if it fails to get  that echo-back within the allotted time. when i/o interface mode is utilized, once the first  uart (0x86) tab bit 7   bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 point a   point b point c point d   i/o interface   (0x30)   tab tcd tcd     tmp19a71   17-37  

 tmp19a71          serial byte has been transmitted, the controll er should send the sclk clock after a certain  idle time to get an acknowledge response. if the received acknowledge response is not 30h, the  controller should give up  further communications.     to select i/o interface mode, the data in the 1s t  byte need not be 30h so long as tab > tcd  is satisfied. the 1st byte may be 91h, a1h, or  b1h; these values generate a falling edge at  point a and point c and a rising edge at point b and point d. when tab > tcd is satisfied and  i/o interface mode is determined, 30h is transmit ted as the 2nd byte (even if the first byte is  not 30h). (here it is assumed that 30h is transmitted as the 1st byte to select i/o interface  mode.)     tmp19a71   17-38 

 tmp19a71              start                                                                                                   figure 17.3.5   s erial operation mode byte reception flow  initialize tmrb0    start prescaler (source clock: imclk/4)     tmrb0 starts counting up point a   stop operation  (infinite loop until reset input)   high-to-low transition  on serial receive pin? yes yes yes low-to-high transition  on serial receive pin? software-capture and save timer value (tab) high-to-low transition  on serial receive pin? software-capture and save timer value (tac) yes low-to-high transition  on serial receive pin? software-capture and save timer value (tad) tmrb0 stops counting  tac    tad? make backup copy of tad value  end yes point b   point c   point d     tmp19a71   17-39  

 tmp19a71              start                             figure 17.3.6   s erial operation mode determination flow      6)   password    the ram transfer command (10h) causes the boot program to perform a password check.  f ollowing an echo-back of the command, the boot program checks the contents of the 12-byte  password area (0x0000_0474 to 0x0000_047f) within the flash memory. as shown in  figure  17.3.7 , if all these address locations contain the same bytes of data other than ffh, a  passwor d area error occurs. in this case, the boot program returns an error acknowledge (11h)  in response to the checksum byte (the 17th  byte) regardless the result of password check.   the  only exception is when the password area is all 00h and the data at the first flash memory  address (0x0000_0000 in single boot mode) is 0x0000_0000. in this case, 12 bytes of 00h in  the password area do not cause a password area error.     the password sequence received from the controller (5th to 16th bytes) is compared to the  passwor d stored in the flash memory.  table 17.3.9  shows how they are compared byte by byte.  all of th e 12 bytes must match to pass the pa ssword check. otherwise, a password error  occurs, which causes the boot program to return an error acknowledg e in response to the  checksum byte (the 17th byte).   tcd    tad  ?  tac tab  >  tcd?   yes uart mode   i/o interface mode    tmp19a71   17-40 

 tmp19a71            start                                       yes are all bytes equal to 00h and  0x0000_ 0000 = 0?   yes   are all bytes the  same?   yes are all bytes equal to ffh?     password area is normal. password area error   figure 17.3.7   password area check flow      table 17.3.9   rel ationship between received bytes and flash memory locations  received byte  compared flash memory data  5th byte  address 0x0000_0474  6th byte  address 0x0000_0475  7th byte  address 0x0000_0476  8th byte  address 0x0000_0477  9th byte  address 0x0000_0478  10th byte  address 0x0000_0479  11th byte  address 0x0000_047a  12th byte  address 0x0000_047b  13th byte  address 0x0000_047c  14th byte  address 0x0000_047d  15th byte  address 0x0000_047e  16th byte  address 0x0000_047f    note:  we recommend setting data other than 0 at address 0x0000_0000 for security reasons.    tmp19a71   17-41  

 tmp19a71          7)  calculation of the show flash memory sum command    the show flash memory sum command adds all 256 kbytes of the flash memory together  and pr ovides the total sum as a word quantity.  the sum is sent to the controller with the  upper 8 bits first, followed by the lower 8 bits.     example:      a1h  b2h  c3h  d4h  in the interests of simplicity, assume the depth of the flash  memory is four locations. then the sum of the four bytes   is calculated as:                 a1h  +  b2h  +  c3h  +  d4h = 02eah    hence, 02h is first sent to the controller, followed by eah.                          8) checksum calculation    the checksum byte for a series of bytes of data is calculated by adding the bytes together,  drop ping the carries, and taking the two?s complement of the total sum. the show flash  memory sum command and the show product  information command perform the checksum  calculation. the controller must perform the same checksum operation in transmitting  checksum bytes.     example:  assume the show flash memory sum command provides the high- and low-order  byt es of the sum as e5h and f6h. to calculate the checksum for a series of e5h and  f6h:    add the bytes together.                 e5h  +  f6h = 1dbh    drop the carry, and then take the two?s complement of the sum. the result is the  che cksum byte.                0  ?  dbh = 25h    tmp19a71   17-42 

 tmp19a71        (7)  general boot program flowchart    figure 17.3.8  shows an overall flowchart of the boot program.     boot program  start         initialize      get sio operation mode data          i/o interface  sio operation  mode?  can be set uart  stop operation   (wait for reset input)  set uart mode and   baud rate  baud rate  setting? set i/o interface mode    cannot be set           ack data     received data (30h)  ack data    received data      show product information  processing  show flash memory sum  processing  transmit routine   (send x1h: command error) transmit routine   (send 30h: normal response) transmit routine  (send 20h: normal response) yes  processed  normall y ?  yes  yes  command error  show product  information? show flash  memory  sum? transmit routine  (send x8h: receive error) ack data    ack data (08h)  ram transfer processing  yes  transmit routine  (send 0x10:normal response)   ack data    received data (10h)  no  receive error?  ram  t ransfer?  prepare ack data  receive routine  get a command  prepare to get a command  (send 30h)  normal response  (send 86h)  normal response                      yes             ack data    received data (20h)  ack data    received data (30h)  ack data    ack data (01h)                      jump to ram          figu re 17.3.8   overall boot program flow    tmp19a71   17-43  

 tmp19a71           (8) handshake operation in i/o interface mode      1)   aft er setting sc2mod0.rxe=1, the tmp19a71 dr ives the p80 pin high and waits for the  sclk2 signal for receiving data.      2)   aft er receiving one byte and generating a re ceive-done interrupt request, the tmp19a71  performs the following sequence of operations:   ?   drives th e p80 pin low to notify  the controller that new data transfer cannot be performed.   ?   p rocesses the received data (ram storage, checksum verification, sum verification, etc.) and  then clears the receive-done interrupt request.  ?   t hen, drives the p80 pin high to notify the cont roller that it is ready to receive new data and  waits for the sclk2 signal for the next receive operation.   in figure 17.3.9, the receive wait time is defined  as  the period between the rising edge of bit 7 of  sclk2 and the next rising edge of the p80 pin.     3)     the next transfer operation should be initiated after a low-to-high transition is confirmed on the  p80 pin. (the controller must optimize the transmit wait time for each transfer format.)      note:  the receive wait time to be inserted after each receive operation varies depending on the operating frequency  and baud rate used and the processing to be performed on received data (checksum verification, ram storage,  password area check, password data check, etc.) .         sclk txd rxd ivr [ 8: 0 ] rxe hs intr 00 intr 0 receive wait time controller (transmit)    tmp19a71 (receive) controller (receive)   tmp19a71 (transmit)   sclk = sclk2, txd = tx2, rxd = rx2, intt = intrx2,   rxe = sc2mod0.rxe, hs = p80    figure 17.3.9   ha ndshake waveform and receive wait time    tmp19a71   17-44 

 tmp19a71          1)   after setting sc2mod0.rxe=0 and setting tr ansmit data in the sc2buf, the tmp19a71  drives the p80 pin high and waits for the sclk2 signal for transmitting data.      2)   aft er transmitting one byte and generating a  transmit-done interrupt request, the tmp19a71  performs the following sequence of operations:   ?   drives th e p80 pin low to notify  the controller that new data transfer cannot be performed.   ?   p erforms required processing on the transmitted data (checksum verification, sum  verification, etc.) and then clears the transmit-done interrupt request.  ?   then, sets sc2 mod0.rxe to 1 and drives the p80 pi n high to notify the controller that it is  ready to receive new data.   in figure 17.3.10, the transmit wait time is defi ne d as the period between the rising edge of bit  7 of sclk2 and the next rising edge of the p80 pin.         the next transfer operation should be initiated after a low-to-high transition is confirmed on the  p80 pin. (the controller must optimize the transmit wait time for each transfer format.)      note:  the transmit wait time to be inserted after each transmit operation varies depending on the operating frequency  and baud rate used and the processing to be performed on transfer data (sc2mod0.rxe setting, checksum  verification, ram storage, password verification, etc.).             sclk = sclk2, txd = tx2, rxd = rx2, intr = inttx2, intt = intrx2,   rxe = sc2mod0.rxe, hs = p80    figure 17.3.10   hand shake waveform and transmit wait time      tmp19a71   17-45  

 tmp19a71          (9)supplementary explanation on determination of a serial operation mode  (transmit waveforms and handshaking in i/o interface mode)    as explained in subsection 5) determination of  a se rial operation mode, each operation command  must send a waveform sa tisfying tab>tcd to select i/o interf ace mode. at this time, point a and  point c should be programmed to be falling edges and point b and point d to be rising edges. if  30h is transmitted as the 1st byte, the boot program must create at least 1 bit of high level after  sending 30h so that a rising edge occurs at poin t d (see figure 17.3.11 below). this measure is  not needed if the data to be sent as the 1st byte  includes a rising edge at point d (e.g. 91h, d9h).  in either case, the serial receive pin must be driven high before entering the procedure for  determining a serial operation mode. (we recommend setting the serial receive pin to high upon  reset.)    in i/o interface mode, the serial receive pin functions as a general-purpose input port for  receivin g the 1st byte. the timing at which i/o inte rface mode is determined  is after a rising edge  at point d, at which point the port pin used for ha ndshaking goes high even if this occurs before  bit 7 is transmitted. (if uart mode is determined , no output is made on the handshake pin.) as  shown in figure 17.3.11 below, the position of po int d varies with the data transmitted as the 1st  byte. after the 1st byte has been transferred, the controller can initiate the transfer of the 2nd  byte after the handshake pin goes high, which indicates that the serial operation mode has been  determined.     transmit data in 1st byte = 30h handshake (hs) pin i/o se tting = after reset state point a point b point c point d point a point b point c point d point a point b point c point d hs rxd hs rxd hs rxd transmit data in 1st byte = 91h transmit data in 1st byte = d9h bit 0bit 1bit 2bit 3 bit 4 bit 5 bit 6 bit 7 extra  bit bit 0bit 1bit 2bit 3bit 4bit 5bit 6bit 7 bit 0bit 1bit 2bit 3bit 4bit 5bit 6bit 7   rxd = rx2, hs = p80  figure 17.3.11   supplementary explanation on determination of a serial operation mode    tmp19a71   17-46 

 tmp19a71        (10) recommended baud rates for the boot program    table 17.3.10  recommended baud rates in single boot mode (uart mode)    prsc = br2cr[5:4], n = br2cr [3:0], k = br2add[3:0]    note 1:  while the serial operation mode is being determined, the baud rate is determined by measuring the waveform  with a timer.  capture value errors generated by the prescaler source clock and division errors that occur in the  serial mode determination flow may make it impossible to set the baud rate.   note 2:  the above table shows expected combinations of frequency and baud rate settings, and other combinations  ma y be used.   note 3:  due to the specifications of the boot program, the fastest baud rate setting allowed is br2cr=02h. the  contr oller must communicate at a baud rate equal to or slower than this setting.        table 17.3.11 recommended baud rate values in single boot mode (i/o interface mode)  operating frequency  (mhz) 56 40 baud rate in i/o interface mode (bps) 2m 1.25m 1m 500k 250k 125k 3m 2.5m 1.25m 1m 500k 250k   note:  when i/o interface mode is selected, a wait time is generated after transmitting/receiving every single byte.           tmp19a71   17-47  

 tmp19a71          (11) other considerations for using the boot program       ?   t he on-chip boot rom inserts one wait state in executing each instruction. in single boot  mode, the pipeline operation for executing each instruction takes twice as long as in the case  of single-chip mode.    ?   no wa it states are inserted while the programming routine transferred to the on-chip ram  is executed on the on-chip ram.   ?   t he boot program updates the values of general-purpose registers upon reset.   ?   t he boot program executes all instructions in 32-bit isa mode. the instruction to be placed  at the first address of the programming routine (i.e., ram storage start address) must be a  32-bit isa instruction.    ?   al l special-purpose registers must be set in the programming routine.  ?   t he boot program uses the general-purpose register r29 (shadow = 0) as the stack pointer.  the r29 is set to 0xffff_bff0 immediately af ter the ram transfer  command is executed.  ?   l ocations other than those to which the programming routine can be transferred with the  ram transfer commend (0xffff_9800 to 0xfff f_afff) are used in the boot program  after reset.  ?   there are  no limitations on ram locations that can be used by the programming routine  stored in the on-chip ram.   ?   whi le the boot program is being executed, all maskable interrupts are disabled.   ?   if m askable interrupts are enabled during execution of the programming routine, the  maskable interrupt vector of the boot program reads the interrupt vector register (ivr) to  obtain the vector address corresponding to the interrupt source, and then transfers control  to this vector address. the value of the general-purpose register r4/r29 (sp) is updated by  executing the routine shown on the following page.  the boot program area does not provide  vector addresses for interrupt  sources and control for clearing interrupt requests. these  should be provided in the programming routine including the setting of the ivr value.      tmp19a71   17-48 

 tmp19a71             interrupts:     addi    sp,   sp,   -4  ; maskable interrupt vector start address     sw    r4,   0( sp )     mfc0    r4,   r13     nop     nop     srl    r4,   r4,   2     andi    r4,   r4,   0x1f     bne    r4,   r0,   the_other ;   if not a maskable interrupt, operation stops     nop       lw    r4,   ivr   ;   read ivr       lw    r4,   0( r4 )    ;   read maskable interrupt vector address       addi    sp,   sp,   4     jr    r4    ;   jump to vector address     nop    the_other:     addi    sp,   sp,   4  the_other_lp:     nop     j    the_other_lp  ;   operation stop loop     nop      note:  after an interrupt is generated, one wait state is inserted for executing each instruction until control jumps to the  v ector address.           ?   nonmask able interrupts must not be used as they  will cause an endless loop in the boot program.  if an endless loop occurs, a reset must be applied.   ?   once contr ol jumps to the programming routine, it should not be returned to the boot program  area except by the above maskable interrupt vector.   ?   init ial settings should be made before the procedure for determining a serial operation mode.  after the reset state is released, an interval of approximately 200 instructions should be inserted  before the transfer of the 1st byte. note that the  1st byte is not transferred via a serial channel.  to detect a falling edge on the serial receive pin, the serial receive pin must be set to high well in  advance of the completion of the above wait interval. (we recommend setting the serial receive  pin to high upon reset.)      tmp19a71   17-49  

 tmp19a71      17.4  on-board programming and erasure  the tmp19a71 flash memory is co ntrolled by commands. in user boot mode and single boot  mode (the ram transfer command), the flash  memory can be programmed and erased by the  tx19a core processor executing so ftware commands. it is the user?s responsibility to create a  program/erase routine. because the flash memory cannot be read while it is being programmed  or erased, the program/erase routine must be executed from the on-chip ram.    17.4.1 key features  program and erase operations on the tmp19a71 flash memory are in principle  controlled by commands. this feature enables program and erase commands to be executed  by accessing particular addresses in the flas h memory. the tx19a core processor issues a  command sequence to the flash memory by  using the 32-bit sw instruction. once a  command sequence is written, the flash memory does not require the tx19a core processor  to provide further controls or timings. the flash memory initiates the embedded program  or erase algorithm automatically. the entire flash memory or one or two flash blocks can be  erased at a time.     table 17.4.1  feature  description  auto program  programs and verifies the desir ed addresses w ord by word automatically.   auto chip erase  erases and verifies t he entire me mory array automatically.   auto block erase  erases and verifies all memory locations in the selected block automatically.   auto multi-block erase  erases and veri fies all memor y locations in multip le selected blocks automatically.   write status flags  provides several  status bits such  as the data polli ng bit and toggle bit, which can be used to  determine whether a program or erase operation is complete or in progress.   anti-programmer security  feature   prevents intrusive access to the flash memory  w hile in programmer mode. protecting both of  the two flash blocks turns on the anti-programmer  security feature. unprotecting both the blocks  turns off the anti-programmer security feature.  this automatically c auses the entire flash  memory to be erased.   block protect  disables program and er ase operations in a f lash block. bl ock-protecting both of the two flash  blocks automatically turns on the ant i-programmer security feature.     bear in mind that, due to the on-chip tx19a core processor interface, the tmp19a71  uses addr esses different from those of the standard flash command sequences.  programming is done word by word; thus the wo rd (32 bits) load instruction should be used  to write to the flash memory. unless otherwise noted, the addresses in the flash memory  are represented as virtual addresses.       tmp19a71   17-50  

 tmp19a71    (1) block architecture  0x0_0000 to 0x1_ffff  128 kbytes  0x2_0000  to 0x3_ffff  128 kbytes  address bits [31:18] vary with the operation mode.     figure 17.4.1   fla sh memory block architecture    (2)  interface between the tx19a core processor and the flash memory  figure 17.4.2  illustrates the internal interface between the tx19a core processor and the  flash m emory in on-board programming modes. the diagram does not show the actual logic  network; instead it is only a conceptual depiction of the interface between the tx19a core  processor and the flash memory.         single-chip mode: 0xbfc0_0000 - 0xbfcf_ffff  single boot mode: 0x0000_0000 - 0x000f_ffff      operation  mode  flash memory      tx19a core processor    (256 kb)  decoder dq31 - dq0    d31- d0  a31 - a16  a16 - a2  ad14 - ad0  ce we oe wr  rd  rdy/bsy reset cpu reset  register                             figure 17.4.2  internal interface between   tx19a core processor and flash memory    tmp19a71   17-51  

 tmp19a71      (3) basic operations  the tmp19a71 flash memory has the fo llo wing two modes of operation:  read mode in which array data is read  ?   ?   ?   ?   embedded operation mode in which the flash array is programmed or erased.    the flash memory enters embedded operation mode when a valid command sequence is  ex ecuted in read mode. in embedded opera tion mode, array data cannot be read.     1) reading array data  t o read array data, the flash memory must  be set to read mode. the flash memory is  automatically set to read mode  upon device power-up, upon reset of the tx19a core processor,  and after an embedded operation is successfully completed. if an embedded operation  terminated abnormally or the flash memory is  required to return to read mode, software  reset or hardware reset is used.     2) writing commands  the tmp19 a71 flash memory is controlled by  commands. a write to the command sequencer  is effected by issuing a command sequence to the flash memory. the flash memory latches the  provided address and data in the command sequ encer and executes the required instructions  (see  table 17.4.4  and  table 17.4.5 ).     t he command sequence being written can be canceled by issuing the read/reset command or  the reset command (software reset). the reset command clears the command sequencer and  resets the flash memory to  read mode. invalid command sequences also cause the flash  memory to clear the command sequen cer and return to  read mode.     3) reset  read/reset command, reset command (software reset)  the flash m emory does not return to read mode automatically if an embedded operation  terminated abnormally. in this case, the read/r eset or reset command mu st be issued to put  the flash memory back in read mode. the read/r eset or reset command may also be written  between sequence cycles of the command being written to clear the contents of the command  sequencer.   hardware reset  as shown in  figure 17.4.2 , the flash memory has a reset pin, which is connected to the reset  signa l of the tx19a core processor. when the system drives the reset pin low or when  certain events such as a watchd og timer time-out causes a reset of the tx19a core processor,  the flash memory immediately terminates any  operation in progress an d is reset to read  mode.   the read/reset and reset commands are also tied to the reset pin to reset the flash  memory to read mode. the embedded operation that was interrupted should be re-initiated  once the flash memory is ready to accept another command sequence because data may be  corrupted.   for a description of the hardware reset operat ion, see section 3.1 reset operation. when a  valid reset is achieved, the tx19a core processor reads the reset exception vector from the  flash memory and services the reset exception.   tmp19a71   17-52  

 tmp19a71      4)  auto program command  a bit must be programmed to change its state  fr om 1 to 0. a bit cannot be programmed from  0 back to 1. only an erase operation can change 0 back to 1.  in user boot mode and the ram transfer command of single boot mode, the auto program  command programs the desired addresses in units of 32 bits (words). the auto program  command requires four bus cycles; the program address and data are written in the fourth  cycle, upon completion of which the program operation will commence. as programming is  performed on a word-by-word basis, the  program address must satisfy a1=a0=0.   it is not possible to program a 32-bit word if some bits have already been written. (this also  app lies when 1 is written in some bits. these  bits must be erased before new data can be  programmed.)  the auto program command executes a sequence of internally timed events to program the  desir ed bits of the addressed memory word and  verify that the desired bits are sufficiently  programmed. the system can determine the status of the programming operation by using  write status flags (see  table 17.4.3 ). any commands written during the programming  op eration are ignored. a hardware reset immediately terminates the programming operation.  the programming operation that was interrupted should be reinitiated once the flash memory  is ready to accept another command sequ ence because data may be corrupted.   the block protection feature disables programming operation in any block. if an attempt is  m ade to program a protected block, the auto program command does nothing; the flash  memory returns to read mode in approximately 3   s after the completion of the fourth bus  cycle of the command sequence.   when the embedded auto program algorithm  is  complete, the flash memory returns to  read mode.   if any failure occurs during the programming operation, the flash memory remains locked  in em bedded operation mode. the system can determine this status by using write status  flags. to put the flash memory back in read  mode, use a software reset to reset the flash  memory or a hardware reset to reset the whole chip. in case of a programming failure, it is  recommended to replace the chip or to discontinue the use of the failing flash block.     tmp19a71   17-53  

 tmp19a71        5)   aut o chip erase command     the auto chip erase command requires six bus cycles. the flash area is partitioned into two  blocks, block 0 and block 1. the chip erase operation is performed for each individual block.  after completion of the sixth bus cycle, the auto chip erase operation will commence  immediately. the embedded auto erase algorithm automatically preprograms the entire  memory for an all-0 data pattern prior to the er ase; then it automatically erases and verifies  the entire memory for an all-1 data pattern. the system can determine the status of the chip  erase operation by using write status flags (see  table 17.4.3 ). any commands written during  the ch ip erase operation are ignored. a hardware reset immediately terminates the chip erase  operation. the chip erase operation that was interrupted should be re-initiated once the flash  memory is ready to accept another command  sequence because data may be corrupted.   the block protection feature disables erase op erations in any block. the auto chip erase  algorithm erases the unprotected blocks and igno res the protected blocks. if both blocks are  protected, the auto chip erase command does  nothing; the flash memory returns to read  mode in approximately 100   s after the completion of the sixth bus cycle of the command  sequence. when the embedded auto chip erase algorithm is complete, the flash memory  returns to read mode.      if any failure occurs during the erase operation, the flash memory remains locked in  embedded operation mode. the system can determine this status by using write status flags.  to put the flash memory back in read mode, use  a software reset or a hardware reset to reset  the flash memory or the device. in case of an erase failure, it is recommended to replace the  chip or discontinue the use of the failing flash block. the failing block can be identified by the  block erase command.     6)   aut o block erase and auto multi-block erase commands     the auto block erase command requires six bus cycles. a time-out begins from the  completion of the command sequence. after a time-out, the erase operation will commence.  the embedded auto block erase algorithm automatically preprograms the selected block for  an all-0 data pattern, and then erases and veri fies that block for an all-1 data pattern.      to erase the next block, the sixth bus cycle must be repeated; the next block address and the  auto block erase command must be provided within the time-out period.     any command other than auto block erase  during the time-out period resets the flash  memory to read mode. the block erase time-out period is 50   s. the system may read dq3 to  determine whether the time-out period has expired. the block erase timer begins counting  upon completion of the sixth bus cycle of the auto block erase command sequence. the  system can determine the status of the erase operation by using write status flags (see  table  17.4.3 ).       any commands written during the block erase operation are ignored. a hardware reset  immediately terminates the block erase operation. the block erase operation that was  interrupted should be re-initiated once the fl ash memory is ready to  accept another command  sequence because data may be corrupted.      the block protection feature disables erase operations in any block. the auto block erase  algorithm erases the unprotected blocks and igno res the protected blocks. if all the selected  blocks are protected, the auto block erase algo rithm does nothing; the flash memory returns  to read mode in approximately 100   s after the final bus cycle of the command sequence.    if any failure occurs during the erase operation, the flash memory remains locked in  embedded operation mode. the system can determine this status by using the write status  flags. to put the flash memory back in read mo de, use a software or ha rdware reset to reset  the flash memory or the whole chip. in case of an erase failure, it is recommended to replace  the chip or discontinue the use of the failing flash block. if any failure occurred during the  tmp19a71   17-54  

 tmp19a71    multi-block erase operation, the failing block can be identified by running auto block erase  on each of the blocks selected for multi-block erasure.    7)  block protect command  the block protection feature disables both prog ra m and erase operations in any block. after  completion of the seventh bus write cycle, the rdy/bsy bit in the flcs register is cleared to  0 during the block protect operation. once the block protect operation is complete, this bit is  set again and the flash memory automa tically returns to read mode.       if any failure occurred during the block protect operation, the flash memory remains locked  in embedded operation mode with flcs.rdy/bsy = 0. to put the flash memory back in  read mode, a software or hardware reset must be executed.     table 17.4.2   ef fects of the program and erase commands on the protected blocks  command  operation  program command on a protected block  no prog ramming  operation is performed, and the flash  memory automatically returns to read mode.  block erase command on a protected block  no eras e ope ration is performed, and the flash memory  automatically returns to read mode.   chip erase command when all the blocks are protected  no  erase ope ration is performed, and the flash memory  automatically returns to read mode.  chip erase command when any blocks are protected  only  th e unprotected blocks are erased. upon completion,  the flash memory automatically returns to read mode.   multi-block erase command when any blocks are protected o nl y the unprotected blocks are erased. upon completion,  the flash memory automatically returns to read mode.          any commands written during the block protect algorithm are ignored. a hardware reset  immediately terminates the block protect operation. the block protect command that was  interrupted should be re-initiated once the fl ash memory is ready to  accept another command  sequence.     8)  block unprotect command   the block unprotect command requires seven bus cycles. after completion of the seventh  bus wri te cycle, the rdy/bsy bit in the flcs register is cleared to 0 during the block  unprotect operation. once the block unprotect operation is complete, this bit is set again and  the flash memory automatically returns to read mode.      if any failure occurred during the block unprotect operation, the flash memory remains  locked in embedded operation mode with flc s.rdy/bsy = 0. to put the flash memory back  in read mode, a software or hard ware reset must be executed.      any commands written during the block unpr otect algorithm are ignored. a hardware reset  immeidately terminates the block unprotect operation. in this case, the block unprotect  operation must be performed again by starting with protecting all the blocks again. use the  verify block protect command to verify the protect status of a block.     9)   v erify block protect command  the verify block protect command is used to verify the protect status of a block. verify block  p rotect is a four-bus-cycle operation. the address of the block to be verified is given in the  fourth cycle. any address within the block range will suffice, provided a[3:0] = 0, a4 = 1 and  a6 = 0. to get correct data, a 32-bit read must be  performed at least twice. use the last read as  valid data. if the selected block is protected, a value of 0x0000_0001 is returned. if the selected  block is not protected, a value of 0x0000_0000 is returned. following the fourth bus cycle, an  tmp19a71   17-55  

 tmp19a71      additional block address may be read.  the verify block protect command does not return the flash memory to read mode. either  the  read/reset command or a hardware reset is  required to reset the flash memory to read  mode or to write the next command.     10) id-read command  the id-read command reads 0x009 8 (fixed) as  toshiba?s manufacturer?s code. the flash  memory address to be read is specified in the fo urth bus read cycle. this  address must satisfy   a[4:0] = 0 and a6 = 0. to get correct data, a 32- bit read must be performed at least twice. use  the last read as valid data. by specifying an address where data other than 0x0098 is stored,  the id-read command can be used to distinguish between the flash-version device (read  value: 0x0098) and the mask-version device (read value: other than 0x0098).   tmp19a71   17-56  

 tmp19a71      11)  write operation status   as shown in  table 17.4.3 , the flash memory provides flag bi ts to  determine the status of an  embedded operation: dq7, dq5 and dq3. these st atus bits can be read during an embedded  operation in the same timing as for read mo de. the flash memory automatically returns to  read mode when an embedded operation completes.  the status of an embedded operation can  be checked by reading the dq7 flag. once an embedded operation completes, the cell data can  be read from the dq7. the dq7 must be read  after checking that an embedded operation has  started (flcs.rdy/bsy=0).   during the embedded program operation, the system must provide the program address  (with a[1:0]  = 0) to read valid status informat ion. during the embedded erase operation, the  system must provide an address (with a[1:0] = 0) within any of the blocks selected for erasure  to read valid status information.  while an embedded operation is in progress, d[ 31: 16] are read as 0. these bits, therefore,  can be used in place of the flcs.rdy/bsy bit in  a system where d[31:16] are not normally 0.  although the flcs register is read as undefined  in the mask-version device, use of d[31:16]  allows the same program to be used in the flash-version and mask-version devices.       table 17.4.3   w rite status flags  status  d7 (dq7)  d5 (dq5)  d3 (dq3)  a uto program  dq7 inverted 0  0  a uto erase  ( during the time-out window)  0 0  0  e mbedded operation  in progress  a uto erase  0  0  1  a uto program  dq7 inverted 1  1  t ime-out in  embedded operation a uto erase  0  1  1  note 1:  while an embedded operation is in progress, d[31:16]=0, d[15:8]=undefined, and dq4, dq2, dq1,  dq0=undefined.  note 2:  while an embedded operation is in progress, dq7 outputs the inverted value of the programmed cell  dat a. during the auto erase operation, dq7 outputs 0 (erased state = 1).     tmp19a71   17-57  

 tmp19a71        dq7 (data polling)  ?   ?   ?   the data polling bit, dq7, indicates the status of  an  embedded operation. data polling is valid  after the final bus write cycle of an embedded command sequence.   when the embedded program algorithm is in pr ogress, an attempt to read  the flash memory  will produce the complement of the data writ ten to dq7. upon completion of the program  algorithm, an attempt to read  the flash memory will produce the true data written to dq7.   when the embedded erase algorithm is in progre ss, an att empt to read the flash memory will  produce a 0 at the dq7 output. upon completion of the erase algorithm, the flash memory will  produce a 1 at the dq7 output.  if any failure occurs during an embedded operation, dq7 continues to output the same value.  thus, dq7  must always be polled in conjunction with the exceeded timing limits (dq5) flag.  (see  table 17.4.3 ).   the flash memory disables address latching when an embedded operation is complete. data  polling must  be performed with a valid progra mmed address or an address within any of the  unprotected blocks selected for erasure.    dq5 (exceeded timing limits)  dq5 produces a 0 while the program or erase op er ation is in progress normally. dq5 produces  a 1 to indicate that the program or erase time has exceeded the specified internal limit. this is  a failure condition that indicates the program or erase cycle was not successfully completed.   the dq5 failure condition also appears if the system tries to program a 1 to a location that was  previously pr ogrammed to a 0. only an erase oper ation can change a 0 back to a 1. in this case,  the embedded program algorithm halts the operation. once the operation has exceeded the  timing limits, dq5 will indicate a 1. note that this is not a device failure condition since the  flash memory was used incorrectly.   under both these conditions, the flash memory remains locked in embedded operation mode.  a  software reset is needed to retu rn the flash memory to read mode.    dq3 (block erase timer)  aft er the completion of the sixth bus cycle of the auto block erase command sequence, the  block erase time-out window of 50   s begins. the erase operation will begin after the time-out  has expired. when the time-out is complete and the erase operation has begun, dq3 switches  from 0 to 1. if dq3 is 0, the flash memory will accept additional auto block erase commands.  each time an auto block erase command is wr itten, the time-out window is reset. dq3  produces a 1 if an embedded operation is not successfully completed.   tmp19a71   17-58  

 tmp19a71      12)  flash control/status register  this is a 32-bit register for monitori n g the status of the flash memory.   in programmer mode, the rdy/bsy output is provided for the host system to monitor  the sta tus of an embedded algorithm. the tx19a core processor can poll the rdy/bsy  bit in the flcs register for the same purpose. the rdy/bsy bit is cleared to 0 when  the flash memory is performing an embedded  operation. the rdy/bsy bit is set to 1  when an embedded operation has completed and the flash memory is ready to accept  the next command. if any failure occurs during an embedded operation, this bit  remains 0. a hardware reset sets this bit to 1.     the rdy/bsy bit is cleared to 0 upon completion of the final bus write cycle of an  embedded operation command, with one exception. in the case of the auto block erase  command, this bit is cleared after the time-out has expired. any command is ignored  while the rdy/bsy bit is cleared.         7  6  5 4  3  2  1 0  flcs bit  sy mbol  D  D   D   D mrom  rdy/bsy  D   D   (0xffff_e520)  read/write  w  r  r  r/w r  r w  r   reset  v alue  0  0   0   0 0  1 0  0    function  must be set  to 0.     must be set  to 0.   0:flash   1:mask  ready/busy  0: busy  1: ready  must be set  to 0.       15  14  13  12  11  10  9  8   bit  sy mbol  D   D   D   D   D   D   D   D     read/write  r  r  r r  r  r  r r   reset  v alue  0   0   0   0   0   0   0   0       23  22  21 20  19  18  17 16   bit  sy mbol  D   D   D   D   D   D   D   D     read/write  r  r  r r  r  r  r r   reset  v alue  0   0   0   0   0   0   0   0       31  30  29 28  27  26  25 24   bit  sy mbol  D   D   D   D   D   D   D   D     read/write  w  r  r r  r  r  r r   reset  v alue  D  0   0   0   0   0   0   0   note 1:  this register must be accessed as a 32-bit quantity.   note 2:   this register does not support bit manipulation instructions.   note 3:   in the mask-version device, the mrom bit is set to 1 and any other bits are read-only with the same  initial v alues.   tmp19a71   17-59  

 tmp19a71        13) flash security  t he tmp19a71 flash memory supports not only on-board programming but also programming  using a general-purpose programmer. therefore, the tmp19a71 flash memory provides a  security feature to prevent intrusive access to  the flash memory while in programmer mode.  the tmp19a71 is secured when both of the two bl ocks are protected, and the contents of the  flash memory cannot be read by a programmer.     turning on the anti-programmer security  fe ature (disabling read accesses)  turning on the anti-programmer security feature disables a general-purpose programmer  from reading the contents of the flash memory. to turn on this feature,   once programming is  complete, protect both the flash blocks. if ei ther one of the blocks is unprotected, the  anti-programmer security feature is off.   in on-board programming modes, the tx19a core processor can read the flash memory even if  the anti-programmer security feature is on. when  the anti-programmer security feature is on,  any reads by programming equipment will always  return a half-word length value of 0x0098.   ?   ?     turning off the anti-programmer securi ty  feature (enabling read accesses)  the anti-programmer security fe ature is designed to disable reads of the flash memory by  programming equipment. while the tmp19a71 is soldered on a board, the tx19a core  processor can always read the flash me mory, regardless of whether or not the  anti-programmer security feature is on. since the flash memory is placed under control of a  user?s application program in on-board operating modes, it is not easy for third parties to  perform intrusive access to the flash memory. therefore, within the confines of a board, the  flash memory does not need to be secured.  the anti-programmer security feature can be  turned off by unprotecting both of the two flash blocks.   prior to turning off the anti-programmer security feature, the flash array is erased  unconditionally. after the flash array is erased, the protect bit of each block is erased to turn  off the anti-programmer security feature. in single-chip mode, block protection is lifted in a  user application program. thus, the flash memo ry is not erased when the anti-programmer  security feature is turned off.  tmp19a71   17-60  

 tmp19a71    (4) command definitions  table 17.4.4   on-board programming mode command definitions         1st bus cycle  (write)         2nd bus cycle  (w rite)          3rd bus cycle  (w rite)           4th bus cycle  (read/write )  command sequence  cycles  required addr. data  addr. data  addr.  data  addr.  data  reset 1  0xxxxx  0x0f0              read/reset 3  0x5554  0x0aa  0x aaa8 0x055  0x5554  0x0f0  ra  rd  auto program  4  0x5554  0x0aa  0xaaa8 0x055  0x5554  0x0a0  pa  pd  auto chip erase  6  0x5554  0x0 aa 0xaaa8  0x055  0x 5554 0x080  0x5554  0xaa  auto block erase  6  0x5554  0x0 aa 0xaaa8  0x055  0x 5554 0x080  0x5554  0xaa  block protect     0x5554 0x0aa  0xaaa8  0x055  0x5554 0x09a  0x5554  0xaa  block unprotect     0x5554 0x0aa  0xaaa8  0x055  0x5554 0x06a  0x5554  0xaa  id read/  block protect verify  4  0x5554 0x0aa  0xaaa8  0x 055 0x5554  0x090  ia  id    (continued from above)         5th bus cycle  (write)          6th bus cycle  (w rite)         7th bus cycle  (w rite)  command sequence  cycles  required addr. data  addr.  data  addr.  data  reset  1             read/reset  3            auto program  4            auto chip erase  6  0xaaa8 0x055  0x5554 0x010      auto block erase  6  0xaaa8 0x055  ba  0x030  ba (note 3) 0x030  block protect  7  0xaaa8 0x055  0x5554 0x09a  bpa  0x09a  block unprotect  7  0xaaa8 0x055  0x5554 0x06a  0x5554  0x06a  id read/block protect  verify  4              note 1:  after every bus write cycle, execute the sync and nop instructions in sequence.  note 2:  in each bus write cycle, bits 16 to 19 should be set to the value coresponding to the flash memory address.   note 3:  for a multi-block erase operation, add ba in the 7th and subsequent bus write cycles.  note 4:  to operate on the flash memory, the watchdog timer must be disabled.    tmp19a71   17-61  

 tmp19a71        the addresses to be provided by the tx19a core processor are shown below.   table 17.4.5 addresses provided by the tx19a core processor   command  address  address: a[23:0]  addr.  a[23:16]  a15  a14  a13  a12  a11 a10 a9  a8 a7 a6  a5  a4 a3  a2 a1  a0 0xxxx0  x  x  x  x  x  x  x  x  x  x x x  0  0  0  0  0x0000  0  0  0  0  0  0  0  0  0  0  0  0 0  0 0  0  0xaaa8  1  0  1  0  1  0  1  0  1  0  1  0 1  0 0  0  0x5554    flash  memory    block  0  1  0  1  0  1  0  1  0  1  0  1 0  1 0  0    (5) miscellaneous  ?   0x0f0, 0 x0aa, 0x055, 0x0a0, 0x080,  0x09a, 0x06a, 0x090, 0x010, 0x030  command sequence write data d[8:0]. to write command data, use a 32-bit (word) load  (sw) instruction with d[31:9] = 0.    ?   r a: read address  any address in the flash me mo ry can be specified.  ?   rd: re ad data  the data at the ra (read address) can be read  b y using an 8-bit (byte) 16-bit (half-word) or  32-bit (word) load instruction.   ?   p a: program address  any flash memory address (a[1:0]=0) to  be pr ogrammed can be specified.  ?   pd: pro gram data  by using a 32-bit (word) sw instruction, the  p a (program address) can be programmed to  the specified data.   ?   ia: id  address  the flash memory address (a[1:0]=0) on which the id-read or verify block protect  co mmand is to be executed.    table 17.4.6   ia  (id address) table   a17  a6  a4  a3  id  id-read (manufacturer?s code)  x  0  0  0  0x0098 (fixed)  0x0000_0001 (block 0 protected)  verify block 0 protect  0  0x0000_0000 (block 0 not protected)  0x0000_0001 (block 1 protected)  verify block 1 protect  1  0 1  0  0x0000_0000 (block 1 not protected)    ?   id: id data   the data that indicates the result of id-read or verify block protect executed on the ia  (id addr ess).     tmp19a71   17-62  

 tmp19a71      ?   ba: block address  the flash memory address (a[1:0]=0) to specify the block to be erased. for example, in user  bo ot mode, block 0 can be selected by executing the lw instruction on an address in the  range of 0xbfc0_0000 to  0xbfc1_ffff (0x0000_0000  0x0001_ffff).     ?   bp a: block protect address  the flash memory address (a[1:0]=0) to specify the block to be protected. for example, in  user bo ot mode, block 0 can be selected by executing the lw instruction on an address in  the range of 0xbfc0_0000  to 0xbfc1_ffff (0x0000_0000  0x0001_ffff).     table 17.4.7   ba  (block address) and bpa (block protect address) table    user boot mode  single boot mode  size  a17  block 0  0xbfc0_0000 to 0xbfc1_ffff  (or 0x0000_0000 to 0x0001_ffff)  0x0000_0000 to 0x0001_ffff 128 kbytes  0  block 1  0xbfc2_0000 to 0xbfc3_ffff  (or 0x0002_0000 to 0x0003_ffff)  0x0002_0000 to 0x0003_ffff   128 kbytes  1    (6) programming examples    (a) programming example for id-read   lui   r4,0x0000   ; r4=0x0000_xxxx   addiu   r4,r4,0x5554  ; r4=0x0000_5554   lui   r5,0x0000   ; r5=0x0000_xxxx   ori   r5,r5,0xaaa8  ; r5=0x0000_aaa8    ori    r6,r0,0 x00aa  ; 1st bus write cycle    sw    r6,0( r4)    ; 1st 0x0000_5554 <-- 0x00aa   sync   nop    ori    r6,r0,0 x0055  ; 2nd bus write cycle    sw    r6,0( r5)    ; 2nd 0x0000_aaa8 <-- 0x0055   sync   nop    ori    r6,r0,0 x0090  ; 3rd bus write cycle    sw    r6,0( r4)    ; 3rd 0x0000_5554 <-- 0x0090   sync   nop    ori    r6,r0,0 x00aa  ; 4th bus read cycle    lw    r7,0( r0)    ; 4th 0x0000_0000(ia:a6=a4=a3=a1=a0 =0) --> r7(dummy)    lw    r7,0( r0)    ; 4th 0x0000_0000(ia:a6=a4=a3=a1=a0 =0) --> r7(dummy)    lw    r7,0( r0)    ; 4th 0x0000_0000(ia:a6=a4=a3=a1=a0 =0) --> r7   sync   nop    tmp19a71   17-63  

 tmp19a71          (b) programming example for polling the flcs.rdy/bsy bit   lui   r7,hi(flcs)   ; r7=0xffff_xxxx    addiu   r7,r7,lo( flcs)  ; r7=0xffff_e520 (flcs address)  rdybsy_lp:   ;  rd y/bsy  poiing    lw    r6,0( r7)    ; r6 <-- flcs    andi    r6,r6,0 x04    ; mask bits other than flcs.rdy/bsy    beq    r6,r0, rdybsy_lp  ; loop until flcs.rdy/bsy=1   nop      (c) programming example for erasing bl ock 1 and  polling the write status flags   lui   r4,0x0002   addiu   r4,r4,0x5554  ; r4=0x0002_5554   lui   r5,0x0002   ori   r5,r5,0xaaa8  ; r5=0x0002_aaa8    ori    r6,r0,0 x00aa  ; 1st bus write cycle    sw    r6,0( r4)    ; 1st 0x0002_5554 <-- 0x00aa   sync   nop    ori    r6,r0,0 x0055  ; 2nd bus write cycle    sw    r6,0( r5)    ; 2nd 0x0002_aaa8 <-- 0x0055   sync   nop    ori    r6,r0,0 x0080  ;3rd bus write cycle    sw    r6,0( r4)    ; 3rd 0x0002_5554 <-- 0x0080   sync   nop    ori    r6,r0,0 x00aa  ; 4th bus write cycle    sw    r6,0( r4)    ; 4th 0x0002_5554 <-- 0x00aa   sync   nop    ori    r6,r0,0 x0055  ; 5th bus write cycle    sw    r6,0( r5)    ; 5th 0x0002_aaa8 <-- 0x0055   sync   nop    ori    r6,r0,0 x0030  ; 6th bus write cycle    sw    r6,0( r5)    ; 6th 0x0002_aaa8(a17=1) <-- 0x0030    sync        ; s tart erasing block 1   nop    dq3_lp:        ; s tart polling the write status flags    lw    r6,0( r5)    ; read data at 0x0002_aaa8  tmp19a71   17-64  

 tmp19a71      andi    r7,r6,0x08    ; mask flags other than dq3    beq    r7,r0,dq3_lp  ; if during the time-out (dq3=0), go to dp3_lp   nop  dq7_lp:    lw    r6,0( r5)    ; read data at 0x0002_aaa8 again    andi    r7,r6,0 x80    ; mask flags other than dq7    bne    r7,r0,da ta_chk  ; if dq7=1, go to data_chk   nop    andi    r7,r6,0 x20     ; mask flags other than mdq5    beq    r7,r0,dq 7_lp  ; if dq5=0 (busy), go to dq7_lp   nop    lw    r6,0( r5)    ; read data at 0x0002_aaa8 again    andi    r7,r6,0 x80    ; mask flags other than dq7    beq    r7,r0,e rase_err  ; if dq7=0, go to error routine   nop  data_chk:   nor   r7,r0,r0   ; r7=0xffff_ffff    lw    r6,0( r5)    ; read data at 0x0002_aaa8 again    beq    r7,r6,complete   ; if erased properly, go to end routine   nop  erase_err:   ori   r6,r0,0x00f0  ; software reset    sw    r6,0( r0)    ; 1st 0x0000_0000 <-- 0x00f0    sync        ; return to  read mode   nop    complete:    (omitted )    ; end routine    note:  these programming examples assume the use of a toshi ba assembler .  if a third-party assembler is used, syntax  errors may occur. change the code as necessary according to the assembler to be used.     tmp19a71   17-65  

 tmp19a71        (7) embedded algorithms          auto program command sequence   (shown below)   last address?   start   no data polling bit  (read as a word quantity)   yes   auto program done   address = address  +  4  (word-by-word)   auto program command sequence (address command) 0x5554(addr.)/0xaa(data)   0xaaa8(addr.)/55h(data)   0x5554(addr.)/a0h(data)   program address (a1, a0 = 0) /  program data (word-by-word))                                                                             figure 17.4.3  auto program operation  tmp19a71   17-66  

 tmp19a71          auto erase command sequence   (shown below)   start data polling bit  (read as a word quantity)   auto erase done   auto chip erase command sequence   (address/command)   0x5554(addr.)/0xaa(data)   0xaaa8(addr.)/0x55(data)   0x5554(addr.)/0x80(data)   0x5554(addr.)/0xaa(data)   0xaaa8(addr.)/0x55(data)   0x5554(addr.)/0x10(data)   auto block/multi-block erase command sequence   (address/command) 0x5554(addr.)/0xaa(data)   0xaaa8(addr.)0x55(data)   0x5554(addr.)/0x80(data)   0x5554(addr.)/0xaa(data)   0xaaa8(addr.)/0x55(data)   block address/0x30(data)   block address/0x30(data)   a dditional addresses  for auto multi-block  erase   (each within 50 s)   block address/0x30(data)                                                                                             figure 17.4.4  auto erase operations  tmp19a71   17-67  

 tmp19a71        start       read a word.  addr. = va   dq5 = 1? yes dq7 = data? read a word.  addr. = va   no yes yes dq7 = data? no   no                                         read a word.  addr. = virtual address         compare with 32-bit quantity.           fail   pass             figure 17.4.5  data polling (dq7) algorithm    tmp19a71   17-68  

 under development         tmp19a71          tmp19a71   18-1 18.  i/o register summary  18.1 register map  i/o registers occupy 16-kbyte addresses from ffffc000h through ffffffffh.     (1) ports    (2)  motor control circuit (pmd: programmable motor driver)     (3)  encoder input circuit    (4)  serial i/o (sio)    (5)  16-bit timer/event counter (tmrb)   (6) watchdog timer    (7)  ad converter    (8) interrupts   (9) clock/standby control    (10) dma controller (dmac)   (11) flash memory  (12)   rom correction      

  tmp19a71          tmp19a71   18-2     [1] ports  address mnemonic  address mnemonic address  mnemonic    address mnemonic  ffffc000h p0d    ffffc010h reserved    ffffc020h reserved    ffffc030h reserved  1h     1h     1h     1h   2h     2h     2h     2h   3h     3h     3h     3h   4h p0cr    4h p0pucr    4h reserved    4h reserved  5h     5h     5h     5h   6h     6h     6h     6h   7h     7h     7h     7h   8h p0ier    8h reserved    8h reserved    8h reserved  9h     9h     9h     9h   ah     ah     ah     ah   bh     bh     bh     bh   ch p0dssr    ch reserved    ch reserved    ch reserved  dh     dh     dh     dh   eh     eh     eh     eh   fh     fh     fh     fh          address mnemonic  address mnemonic  address mnemonic    address mnemonic  ffffc040h p1d    ffffc050h reserved  ffffc060h reserved    ffffc070h reserved  1h     1h   1h     1h   2h     2h   2h     2h   3h     3h   3h     3h   4h p1cr    4h p1pucr  4h reserved    4h reserved  5h     5h   5h     5h   6h     6h   6h     6h   7h     7h   7h     7h   8h p1ier    8h reserved  8h reserved    8h reserved  9h     9h   9h     9h   ah     ah   ah     ah   bh     bh   bh     bh   ch p1dssr    ch reserved  ch reserved    ch reserved  dh     dh   dh     dh   eh     eh   eh     eh   fh     fh   fh     fh     address mnemonic  address mnemonic address mnemonic    address mnemonic  ffffc080h p2d   ffffc090h reserved  ffffc0a0h reserved    ffffc0b0h reserved  1h     1h   1h     1h   2h     2h   2h     2h   3h     3h   3h     3h   4h p2cr    4h p2pucr  4h reserved    4h reserved  5h     5h   5h     5h   6h     6h   6h     6h   7h     7h   7h     7h   8h p2ier    8h reserved  8h reserved    8h reserved  9h     9h   9h     9h   ah     ah   ah     ah   bh     bh   bh     bh   ch p2dssr    ch reserved  ch reserved    ch reserved  dh     dh   dh     dh   eh     eh   eh     eh   fh     fh   fh     fh          

 under development         tmp19a71          tmp19a71   18-3   address mnemonic  address mnemonic address mnemonic    address mnemonic  ffffc0c0h p3d  ffffc0d0h reserved  ffffc0e0h reserved    ffffc0f0h reserved  1h   1h   1h     1h   2h   2h   2h     2h   3h   3h   3h     3h   4h p3cr  4h p3pucr  4h reserved    4h reserved  5h   5h   5h     5h   6h   6h   6h     6h   7h   7h   7h     7h   8h p3ier  8h reserved  8h reserved    8h reserved  9h   9h   9h     9h   ah   ah   ah     ah   bh   bh   bh     bh   ch p3dssr  ch reserved  ch reserved    ch reserved  dh   dh   dh     dh   eh   eh   eh     eh   fh   fh   fh     fh      address mnemonic  address mnemonic address  mnemonic    address mnemonic  ffffc100h reserved    ffffc110h reserved    ffffc120h reserved    ffffc130h reserved  1h     1h     1h     1h   2h     2h     2h     2h   3h     3h     3h     3h   4h reserved    4h reserved    4h reserved    4h reserved  5h     5h     5h     5h   6h     6h     6h     6h   7h     7h     7h     7h   8h reserved    8h reserved    8h reserved    8h reserved  9h     9h     9h     9h   ah     ah     ah     ah   bh     bh     bh     bh   ch reserved    ch reserved    ch reserved    ch reserved  dh     dh     dh     dh   eh     eh     eh     eh   fh     fh     fh     fh          address mnemonic  address mnemonic  address mnemonic    address mnemonic  ffffc140h p5d    ffffc150h reserved  ffffc160h reserved    ffffc170h reserved  1h     1h   1h     1h   2h     2h   2h     2h   3h     3h   3h     3h   4h reserved    4h p5pucr  4h reserved    4h reserved  5h     5h   5h     5h   6h     6h   6h     6h   7h     7h   7h     7h   8h p5ier    8h p5fr  8h reserved    8h reserved  9h     9h   9h     9h   ah     ah   ah     ah   bh     bh   bh     bh   ch reserved    ch reserved  ch reserved    ch reserved  dh     dh   dh     dh   eh     eh   eh     eh   fh     fh   fh     fh     

  tmp19a71          tmp19a71   18-4     address mnemonic  address mnemonic address mnemonic    address mnemonic  ffffc180h p6d   ffffc190h reserved  ffffc1a0h reserved    ffffc1b0h reserved  1h     1h   1h     1h   2h     2h   2h     2h   3h     3h   3h     3h   4h p6cr    4h p6pucr  4h reserved    4h reserved  5h     5h   5h     5h   6h     6h   6h     6h   7h     7h   7h     7h   8h p6ier    8h p6fr  8h reserved    8h reserved  9h     9h   9h     9h   ah     ah   ah     ah   bh     bh   bh     bh   ch p6dssr    ch reserved  ch reserved    ch reserved  dh     dh   dh     dh   eh     eh   eh     eh   fh     fh   fh     fh          address mnemonic  address mnemonic address mnemonic    address mnemonic  ffffc1c0h p7d  ffffc1d0h reserved  ffffc1e0h reserved    ffffc1f0h reserved  1h   1h   1h     1h   2h   2h   2h     2h   3h   3h   3h     3h   4h p7cr  4h p7pucr  4h reserved    4h reserved  5h   5h   5h     5h   6h   6h   6h     6h   7h   7h   7h     7h   8h p7ier  8h p7fr1  8h reserved    8h reserved  9h   9h   9h     9h   ah   ah   ah     ah   bh   bh   bh     bh   ch p7dssr  ch p7fr2  ch reserved    ch reserved  dh   dh   dh     dh   eh   eh   eh     eh   fh   fh   fh     fh     address mnemonic  address mnemonic address  mnemonic    address mnemonic  fffc200h p8d    ffffc210h p8odcr    ffffc220h reserved    ffffc230h reserved  1h     1h     1h     1h   2h     2h     2h     2h   3h     3h     3h     3h   4h p8cr    4h p8pucr    4h reserved    4h reserved  5h     5h     5h     5h   6h     6h     6h     6h   7h     7h     7h     7h   8h p8ier    8h p8fr    8h reserved    8h reserved  9h     9h     9h     9h   ah     ah     ah     ah   bh     bh     bh     bh   ch p8dssr    ch reserved    ch reserved    ch reserved  dh     dh     dh     dh   eh     eh     eh     eh   fh     fh     fh     fh          

 under development         tmp19a71          tmp19a71   18-5   address mnemonic  address mnemonic  address mnemonic    address mnemonic  ffffc240h p9d    ffffc250h reserved  ffffc260h p9ecr    ffffc270h reserved  1h     1h   1h     1h   2h     2h   2h     2h   3h     3h   3h     3h   4h p9cr    4h p9pucr  4h p9eclr    4h reserved  5h     5h   5h     5h   6h     6h   6h     6h   7h     7h   7h     7h   8h p9ier    8h p9fr1  8h reserved    8h reserved  9h     9h   9h     9h   ah     ah   ah     ah   bh     bh   bh     bh   ch p9dssr    ch p9fr2  ch reserved    ch reserved  dh     dh   dh     dh   eh     eh   eh     eh   fh     fh   fh     fh     address mnemonic  address mnemonic address mnemonic    address mnemonic  ffffc280h pad   ffffc290h reserved ffffc2a0h paeclr    ffffc2b0h reserved  1h     1h   1h     1h   2h     2h   2h     2h   3h     3h   3h     3h   4h pacr    4h papucr  4h reserved    4h reserved  5h     5h   5h     5h   6h     6h   6h     6h   7h     7h   7h     7h   8h paier    8h pafr  8h reserved    8h reserved  9h     9h   9h     9h   ah     ah   ah     ah   bh     bh   bh     bh   ch padssr    ch paecr  ch reserved    ch reserved  dh     dh   dh     dh   eh     eh   eh     eh   fh     fh   fh     fh          address mnemonic  address mnemonic address mnemonic    address mnemonic  ffffc2c0h pbd  ffffc2d0h reserved ffffc2e0h pbeclr    ffffc2f0h reserved  1h   1h   1h     1h   2h   2h   2h     2h   3h   3h   3h     3h   4h pbcr  4h pbpucr  4h reserved    4h reserved  5h   5h   5h     5h   6h   6h   6h     6h   7h   7h   7h     7h   8h pbier  8h pbfr  8h reserved    8h reserved  9h   9h   9h     9h   ah   ah   ah     ah   bh   bh   bh     bh   ch pbdssr  ch pbecr  ch reserved    ch reserved  dh   dh   dh     dh   eh   eh   eh     eh   fh   fh   fh     fh   

  tmp19a71          tmp19a71   18-6    [2] pmd  address mnemonic  address mnemonic address mnemonic   address mnemonic ffffc300h mdcr0    ffffc310h cmpv0    ffffc320h emgcr0    ffffc330 trgcmp02 1h     1h     1h     1h   2h     2h     2h     2h   3h     3h     3h     3h   4h mdcnt0    4h cmpw0    4h trgcr0    4h reserved  5h     5h     5h     5h   6h     6h     6h     6h   7h     7h     7h     7h   8h mdprd0    8h mdout0    8h trgcmp00    8h   9h     9h     9h     9h   ah     ah     ah     ah   bh     bh     bh     bh   ch cmpu0    ch emgrel0    ch trgcmp01    ch   dh     dh     dh     dh   eh     eh     eh     eh   fh     fh     fh     fh     address mnemonic  address  mnemonic  address  mnemonic  address mnemonic ffffc340h mdcr1    ffffc350h cmpv1  ffffc360h emgcr1    ffffc370 trgcmp12 1h     1h   1h     1h   2h     2h   2h     2h   3h     3h   3h     3h   4h mdcnt1    4h cmpw1  4h trgcr1    4h reserved  5h     5h   5h     5h   6h     6h   6h     6h   7h     7h   7h     7h   8h mdprd1    8h mdout1  8h trgcmp10    8h   9h     9h   9h     9h   ah     ah   ah     ah   bh     bh   bh     bh   ch cmpu1    ch emgrel1  ch trgcmp11    ch   dh     dh   dh     dh   eh     eh   eh     eh   fh     fh   fh     fh      [3] abz encoder  address mnemonic  address  mnemonic  address  mnemonic   ffffc400h entncr    ffffc410h reserved  ffffc420h     1h     1h   1h     2h     2h   2h     3h     3h   3h     4h enreload   4h   4h     5h     5h   5h     6h     6h   6h     7h     7h   7h     8h enint    8h   8h     9h     9h   9h     ah     ah   ah     bh     bh   bh     ch encnt    ch   ch     dh     dh   dh     eh     eh   eh     fh     fh   fh       

 under development         tmp19a71          tmp19a71   18-7 [4] sio  address mnemonic  address  mnemonic  address  mnemonic  address mnemonic ffffc480h sc0mod0    ffffc490h sc0buf  ffffc4a0h sc1mod0   ffffc4b0h sc1buf  1h sc0mod1    1h   1h sc1mod1    1h   2h     2h   2h     2h   3h     3h   3h     3h   4h sc0cr    4h sc0fcnf  4h sc1cr    4h sc1fcnf  5h sc0mod2    5h   5h sc1mod2    5h   6h     6h   6h     6h   7h     7h   7h     7h   8h br0cr    8h sc0ftc  8h br1cr    8h sc1ftc  9h br0add    9h sc0frc  9h br1add    9h sc1frc  ah     ah   ah     ah   bh     bh   bh     bh   ch     ch sc0fts  ch     ch sc1fts  dh     dh sc0frs  dh     dh sc1frs  eh     eh   eh     eh   fh     fh   fh     fh     address mnemonic  address mnemonic  address  mnemonic  address mnemonic ffffc4c0h sc2mod0    ffffc4d0h sc2buf  ffffc4e0h sc3mod0    ffffc4f0h sc3buf  1h sc2mod1    1h   1h sc3mod1    1h   2h     2h   2h     2h   3h     3h   3h     3h   4h sc2cr    4h sc2fcnf  4h sc3cr    4h sc3fcnf  5h sc2mod2    5h   5h sc3mod2    5h   6h     6h   6h     6h   7h     7h   7h     7h 8h br2cr    8h sc2ftc  8h br3cr    8h sc3ftc  9h br2add    9h sc2frc  9h br3add    9h sc3frc  ah     ah   ah     ah   bh     bh   bh     bh   ch     ch sc2fts  ch     ch sc3fts  dh     dh sc2frs  dh     dh sc3frs  eh     eh   eh     eh   fh     fh   fh     fh     [5] tmrb   address mnemonic  address  mnemonic  address  mnemonic  address mnemonic ffffc700h tb0run    ffffc710h tb0reg1  ffffc720h tb1run    ffffc730h tb1reg1  1h     1h   1h     1h   2h     2h   2h     2h   3h     3h   3h     3h   4h tb0mod(l)    4h tb0cp0  4h tb1mod(l)    4h tb1cp0  5h (tb0modh)   5h   5h (tb1modh)    5h   6h     6h   6h     6h   7h     7h   7h     7h   8h tb0ff    8h tb0cp1  8h tb1ff    8h reserved  9h     9h   9h     9h   ah     ah   ah     ah   bh     bh   bh     bh   ch tb0reg0    ch tb0cnt  ch tb1reg0    ch tb1cnt  dh     dh   dh     dh   eh     eh   eh     eh   fh     fh   fh     fh     

  tmp19a71          tmp19a71   18-8     address mnemonic  address mnemonic address mnemonic  address mnemonic  ffffc740h tb2run   ffffc750h tb2reg1    ffffc760h tb3run   ffffc770h tb3reg1  1h     1h     1h     1h   2h     2h     2h     2h   3h     3h     3h     3h   4h tb2mod(l)    4h tb2cp0    4h tb3mod(l)    4h tb3cp0  5h (tb2modh)    5h     5h (tb3modh)    5h   6h     6h     6h     6h   7h     7h     7h     7h   8h tb2ff    8h reserved    8h tb3ff    8h reserved  9h     9h     9h     9h   ah     ah     ah     ah   bh     bh     bh     bh   ch tb2reg0    ch tb2cnt    ch tb3reg0    ch tb3cnt  dh     dh     dh     dh   eh     eh     eh     eh   fh     fh     fh     fh     [6] wdt  address mnemonic ffffc830h wdmod(l) 1h (wdmodh) 2h   3h   4h wdcr  5h   6h   7h   8h wdcnt  9h   ah   bh   ch   dh   eh   fh     [7-1] adc (normal mode)  address mnemonic  address mnemonic address  mnemonic    address mnemonic  ffffc900h adnres0    ffffc910h adnres4    ffffc920h adchpr0    ffffc930h adchpc0  1h     1h     1h     1h   2h     2h     2h     2h   3h     3h     3h     3h   4h adnres1    4h adnres5    4h adnmod0(l)    4h adcmp00  5h     5h     5h (adnmod0h)    5h   6h     6h     6h     6h   7h     7h     7h     7h   8h adnres2    8h adnres6    8h adnclk0    8h adcmp01  9h     9h     9h     9h   ah     ah     ah     ah   bh     bh     bh     bh   ch adnres3    ch adnres7    ch cmpctl0(l)    ch adcbasn0  dh     dh     dh (cmpctl0h)    dh   eh     eh     eh     eh   fh     fh     fh     fh          

 under development         tmp19a71          tmp19a71   18-9   address mnemonic  ffffc940h adcstart0 1h   2h   3h   4h   5h   6h   7h   8h   9h   ah   bh   ch   dh   eh   fh     address mnemonic  address mnemonic  address  mnemonic    address mnemonic  ffffc980h adnres8    ffffc990h adnres12  ffffc9a0h adchpr1    ffffc9b0h adchpc1  1h     1h   1h     1h   2h     2h   2h     2h   3h     3h   3h     3h   4h adnres9    4h adnres13  4h adnmod1(l)    4h adcmp10  5h     5h   5h (adnmod1h)    5h   6h     6h   6h     6h   7h     7h   7h     7h   8h adnres10    8h adnres14  8h adnclk1    8h adcmp11  9h     9h   9h     9h   ah     ah   ah     ah   bh     bh   bh     bh   ch adnres11    ch adnres15  ch cmpctl1(l)    ch adcbasn1  dh     dh   dh (cmpctl1h)    dh   eh     eh   eh     eh   fh     fh   fh     fh     address mnemonic  ffffc9c0h adcstart1 1h   2h   3h   4h   5h   6h   7h   8h   9h   ah   bh   ch   dh   eh   fh     

  tmp19a71          tmp19a71   18-10    [7-2] adc (pmd mode)  address mnemonic  address mnemonic address mnemonic   address mnemonic ffffcd00h adpres0    ffffcd10h adpres4  ffffcd20h reserved    ffffcd30h reserved  1h     1h   1h     1h   2h     2h   2h     2h   3h     3h   3h     3h   4h adpres1    4h adpres5  4h reserved    4h reserved  5h     5h   5h     5h   6h     6h   6h     6h   7h     7h   7h     7h   8h adpres2    8h adpres6  8h reserved    8h reserved  9h     9h   9h     9h   ah     ah   ah     ah   bh     bh   bh     bh   ch adpres3    ch adpres7  ch reserved    ch reserved  dh     dh   dh     dh   eh     eh   eh     eh   fh     fh   fh     fh     address mnemonic  address mnemonic  address mnemonic  address mnemonic  ffffcd40h adcsett00(l)  ffffcd50h reserved  ffffcd60h adpmod01(l)  ffffcd70h admodsel0 1h (adcsett00h)  1h   1h (adpmod01h)  1h   2h   2h   2h   2h   3h   3h   3h   3h   4h reserved  4h reserved  4h adcne0(l)  4h   5h   5h   5h (adcne0h)  5h   6h   6h   6h   6h   7h   7h   7h   7h   8h adcset00(l)  8h adpclk0  8h adcnt0  8h   9h (adcset00h) 9h   9h   9h   ah   ah   ah   ah   bh   bh   bh   bh   ch adcset01(l)  ch adpmod00  ch adcbasp0  ch   dh (adcset01h) dh   dh   dh   eh   eh   eh   eh   fh   fh   fh   fh     address mnemonic  address mnemonic  address mnemonic  address mnemonic ffffcd80h adpres8    ffffc d90h adpres12 ffffcda0h adpr es16  ffffcdb0h reserved  1h     1h   1h     1h   2h     2h   2h     2h   3h     3h   3h     3h   4h adpres9    4h adpres13  4h adpres17    4h reserved  5h     5h   5h     5h   6h     6h   6h     6h   7h     7h   7h     7h   8h adpres10    8h adpres14  8h adpres18    8h reserved  9h     9h   9h     9h   ah     ah   ah     ah   bh     bh   bh     bh   ch adpres11    ch adpres15  ch reserved    ch reserved  dh     dh   dh     dh   eh     eh   eh     eh   fh     fh   fh     fh     

 under development         tmp19a71          tmp19a71   18-11   address mnemonic  address mnemonic  address mnemonic  address mnemonic  ffffcdc0h adcsett10(l)  ffffcdd0h adcset12(l) ffffcde0h adpmod11(l)  ffffcdf0h admodsel1 1h (adcsett10h)  1h (adcset12h) 1h (adpmod11h)  1h   2h   2h   2h   2h   3h   3h   3h   3h   4h adcsett11  4h reserved  4h adcne1(l)  4h   5h   5h   5h (adcne1h)  5h   6h   6h   6h   6h   7h   7h   7h   7h   8h adcset10(l)  8h adpclk1  8h adcnt1  8h   9h (adcset10h)  9h   9h   9h   ah   ah   ah   ah   bh   bh   bh   bh   ch adcset11(l)  ch adpmod10  ch adcbasp1  ch   dh (adcset11h)  dh   dh   dh   eh   eh   eh   eh   fh   fh   fh   fh     [8] irc  address mnemonic  address mnemonic address  mnemonic    address mnemonic  ffffd000h imr00    ffffd010h imr16    ffffd020h imr32    ffffd030h imr48  1h (imr01)    1h (imr17)    1h (imr33)    1h (imr49)  2h (imr02)    2h (imr18)    2h (imr34)    2h (imr50)  3h (imr03)    3h (imr19)    3h (imr35)    3h (imr51)  4h imr04    4h imr20    4h imr36    4h imr52  5h (imr05)    5h (imr21)    5h (imr37)    5h (imr53)  6h (imr06)    6h (imr22)    6h (imr38)    6h (imr54)  7h (imr07)    7h (imr23)    7h (imr39)    7h (imr55)  8h imr08    8h imr24    8h imr40    8h imr56  9h (imr09)    9h (imr25)    9h (imr41)    9h (imr57)  ah (imr10)    ah (imr26)    ah (imr42)    ah (imr58)  bh (imr11)    bh (imr27)    bh (imr43)    bh (imr59)  ch imr12    ch imr28    ch imr44    ch imr60  dh (imr13)    dh (imr29)    dh (imr45)    dh (imr61)  eh (imr14)    eh (imr30)    eh (imr46)    eh (imr62)  fh (imr15)    fh (imr31)    fh (imr47)    fh (imr63)         address mnemonic  address mnemonic  address mnemonic    address mnemonic  ffffd040h imr64    ffffd050h imr80  ffffd080h ivr    ffffd070h   1h (imr65)    1h (imr81)  1h     1h   2h (imr66)    2h (imr82)  2h     2h   3h (imr67)    3h (imr83)  3h     3h   4h imr68    4h imr84  4h iclr    4h   5h (imr69)    5h (imr85)  5h     5h   6h (imr70)    6h (imr86)  6h     6h   7h (imr71)    7h (imr87)  7h     7h   8h imr72    8h imr88  8h ilev    8h   9h (imr73)    9h (imr89)  9h     9h   ah (imr74)    ah (imr90)  ah     ah   bh (imr75)    bh (imr91)  bh     bh   ch imr76    ch imr92  ch     ch   dh (imr77)    dh (imr93)  dh     dh   eh (imr78)    eh (imr94)  eh     eh   fh (imr79)    fh (imr95)  fh     fh     

  tmp19a71          tmp19a71   18-12     [9] clock generator  address mnemonic  address mnemonic address mnemonic    address mnemonic  ffffd300h clkact   ffffd310h clknmi    ffffd320h reserved    ffffd330h reserved  1h     1h reserved    1h reserved    1h   2h     2h clkw0    2h     2h   3h     3h reserved    3h     3h   4h clkosc    4h reserved    4h     4h   5h clkwut    5h reserved    5h     5h   6h clkspd    6h reserved    6h     6h   7h clkprsc    7h reserved    7h     7h   8h reserved    8h reserved    8h     8h   9h reserved    9h reserved    9h     9h   ah reserved    ah clkint0    ah     ah   bh     bh clkint1    bh     bh   ch reserved    ch clkint2    ch     ch   dh clkmisc    dh clkint3    dh     dh   eh     eh reserved    eh     eh   fh     fh reserved    fh     fh          [10] modec  address mnemonic  address mnemonic address mnemonic    address mnemonic  ffffd400h modecr   ffffd410h     ffffd420h     ffffd430h   1h     1h     1h     1h   2h     2h     2h     2h   3h     3h     3h     3h   4h     4h     4h     4h   5h     5h     5h     5h   6h     6h     6h     6h   7h     7h     7h     7h   8h     8h     8h     8h   9h     9h     9h     9h   ah     ah     ah     ah   bh     bh     bh     bh   ch     ch     ch     ch   dh     dh     dh     dh   eh     eh     eh     eh   fh     fh     fh     fh           [11] dmac  address mnemonic  address mnemonic address mnemonic  address mnemonic ffffd600h ccr0(ll)   ffffd610h bcr0(ll)   ffffd620h ccr1(ll)   ffffd630h bcr1(ll)  1h  (ccr0lh)  1h (bcr0lh)  1h (ccr1lh)  1h (bcr1lh)  2h  (ccr0hl)  2h (bcr0hl)  2h (ccr1hl)  2h (bcr1hl)  3h  (ccr0hh)  3h (bcr0hh)  3h (ccr1hh)  3h (bcr1hh)  4h  csr0(ll)  4h    4h csr1(ll)  4h   5h  (csr0lh)  5h    5h (csr1lh)  5h   6h  (csr0hl)  6h    6h (csr1hl)  6h   7h  (csr0hh)  7h    7h (csr1hh)  7h   8h  sar0(ll)  8h dtcr0(ll)  8h sar1(ll)  8h dtcr1(ll) 9h  (sar0lh)  9h (dtcr0lh)  9h (sar1lh)  9h (dtcr1lh) ah (sar0hl)  ah (dtcr0hl)  ah (sar1hl)  ah (dtcr1hl) bh (sar0hh)    bh (dtcr0hh)   bh (sar1hh)   bh (dtcr1hh) ch dar0(ll)  ch    ch dar1(ll)  ch   dh (dar0lh)  dh    dh (dar1lh)  dh   eh (dar0hl)  eh    eh (dar1hl)  eh   fh  (dar0hh)  fh    fh (dar1hh)  fh     

 under development         tmp19a71          tmp19a71   18-13 address mnemonic  address mnemonic address mnemonic  address mnemonic ffffd640h ccr2(ll)   ffffd650h bcr2(ll)   ffffd660h ccr3(ll)   ffffd670h bcr3(ll)  1h  (ccr2lh)  1h (bcr2lh)  1h (ccr3lh)  1h (bcr3lh)  2h  (ccr2hl)  2h (bcr2hl)  2h (ccr3hl)  2h (bcr3hl)  3h  (ccr2hh)  3h (bcr2hh)  3h (ccr3hh)  3h (bcr3hh)  4h  csr2(ll)  4h    4h csr3(ll)  4h   5h  (csr2lh)  5h    5h (csr3lh)  5h   6h  (csr2hl)  6h    6h (csr3hl)  6h   7h  (csr2hh)  7h    7h (csr3hh)  7h   8h  sar2(ll)  8h dtcr2(ll)  8h sar3(ll)  8h dtcr3(ll) 9h  (sar2lh)  9h (dtcr2lh)  9h (sar3lh)  9h (dtcr3lh) ah (sar2hl)  ah (dtcr2hl)  ah (sar3hl)  ah (dtcr3hl) bh (sar2hh)    bh (dtcr2hh)   bh (sar3hh)   bh (dtcr3hh) ch dar2(ll)  ch    ch dar3(ll)  ch   dh (dar2lh)  dh    dh (dar3lh)  dh   eh (dar2hl)  eh    eh (dar3hl)  eh   fh  (dar2hh)  fh    fh (dar3hh)  fh       address mnemonic  address mnemonic address mnemonic  address mnemonic ffffd680h ccr4(ll)    ffffd690h bcr4(ll)   ffffd6a0h ccr5(ll)   ffffd6b0h bcr5(ll)  1h  (ccr4lh)  1h (bcr4lh)  1h (ccr5lh)  1h (bcr5lh)  2h  (ccr4hl)  2h (bcr4hl)  2h (ccr5hl)  2h (bcr5hl)  3h  (ccr4hh)  3h (bcr4hh)  3h (ccr5hh)  3h (bcr5hh)  4h  csr4(ll)  4h    4h csr5(ll)  4h   5h  (csr4lh)  5h    5h (csr5lh)  5h   6h  (csr4hl)  6h    6h (csr5hl)  6h   7h  (csr4hh)  7h    7h (csr5hh)  7h   8h  sar4(ll)  8h dtcr4(ll)  8h sar5(ll)  8h dtcr5(ll) 9h  (sar4lh)  9h (dtcr4lh)  9h (sar5lh)  9h (dtcr5lh) ah (sar4hl)  ah (dtcr4hl)  ah (sar5hl)  ah (dtcr5hl) bh (sar4hh)    bh (dtcr4hh)   bh (sar5hh)   bh (dtcr5hh) ch dar4(ll)  ch    ch dar5(ll)  ch   dh (dar4lh)  dh    dh (dar5lh)  dh   eh (dar4hl)  eh    eh (dar5hl)  eh   fh  (dar4hh)  fh    fh (dar5hh)  fh     address mnemonic  address mnemonic address mnemonic  address mnemonic ffffd6c0h ccr6(ll)    ffffd6d0h bcr6(ll)  ffffd6e0h ccr7(ll)    ffffd6f0h bcr7(ll)  1h (ccr6lh)    1h (bcr6lh)  1h (ccr7lh)    1h (bcr7lh)  2h (ccr6hl)    2h (bcr6hl)  2h (ccr7hl)    2h (bcr7hl)  3h (ccr6hh)    3h (bcr6hh)  3h (ccr7hh)    3h (bcr7hh)  4h csr6(ll)    4h   4h csr7(ll)    4h   5h (csr6lh)    5h   5h (csr7lh)    5h   6h (csr6hl)    6h   6h (csr7hl)    6h   7h (csr6hh)    7h   7h (csr7hh)    7h   8h sar6(ll)    8h dtcr6(ll) 8h sar7(ll)    8h dtcr7(ll) 9h (sar6lh)    9h (dtcr6lh) 9h (sar7lh)    9h (dtcr7lh) ah (sar6hl)    ah (dtcr6hl) ah (sar7hl)    ah (dtcr7hl) bh (sar6hh)    bh (dtcr6hh ) bh (sar7hh)   bh (dtcr7hh) ch dar6(ll)    ch   ch dar7(ll)    ch   dh (dar6lh)    dh   dh (dar7lh)    dh   eh (dar6hl)    eh   eh (dar7hl)    eh   fh (dar6hh)    fh   fh (dar7hh)    fh     

  tmp19a71          tmp19a71   18-14     address mnemonic  address mnemonic address mnemonic  address mnemonic ffffd700h  dcr(ll)  ffffd710h   ffffd720h   ffffd730h   1h  (dcrlh)  1h   1h   1h   2h  (dcrhl)  2h   2h   2h   3h  (dcrhh)  3h   3h   3h   4h  reserved  4h   4h   4h   5h  reserved  5h   5h   5h   6h  reserved  6h   6h   6h   7h  reserved  7h   7h   7h   8h    8h   8h   8h   9h    9h   9h   9h   ah    ah   ah   ah   bh    bh   bh   bh   ch  dhr(ll)  ch   ch   ch   dh  (dhrlh)  dh   dh   dh   eh  (dhrhl)  eh   eh   eh   fh  (dhrhh)  fh   fh   fh       address mnemonic  address mnemonic address mnemonic  address mnemonic ffffd740h    ffffd750h   ffffd760h   ffffd770h   1h    1h   1h   1h   2h    2h   2h   2h   3h    3h   3h   3h   4h    4h   4h   4h   5h    5h   5h   5h   6h    6h   6h   6h   7h    7h   7h   7h   8h    8h   8h   8h   9h    9h   9h   9h   ah    ah   ah   ah   bh    bh   bh   bh   ch    ch   ch   ch   dh    dh   dh   dh   eh    eh   eh   eh   fh    fh   fh   fh     

 under development         tmp19a71          tmp19a71   18-15   [12] flash memory (flash version only; dma not supported)  address mnemonic  address mnemonic address mnemonic ffffe510h seqmod    ffffe520h flcs    ffffe530h b0dcr  1h     1h     1h   2h     2h     2h   3h     3h     3h   4h seqcnt    4h     4h b0dlr  5h     5h     5h   6h     6h     6h   7h     7h     7h   8h reserved    8h     8h b1dcr  9h     9h     9h   ah     ah     ah   bh     bh     bh   ch reserved    ch     ch b1dlr  dh     dh     dh   eh     eh     eh   fh     fh     fh   [13] rom correction (dma not supported)  address mnemonic  address mnemonic address mnemonic  address mnemonic ffffe540h addreg0    ffffe550h addreg4   ffffe560h reserved   ffffe570h reserved  1h    1h   1h   1h   2h    2h   2h   2h   3h    3h   3h   3h   4h addreg1    4h addreg5    4h reserved    4h reserved  5h    5h   5h   5h   6h    6h   6h   6h   7h    7h   7h   7h   8h addreg2    8h addreg6    8h reserved    8h reserved  9h    9h   9h   9h   ah    ah   ah   ah   bh    bh   bh   bh   ch addreg3    ch addreg7    ch reserved    ch reserved  dh    dh   dh   dh   eh    eh   eh   eh   fh    fh   fh   fh     

  tmp19a71          tmp19a71   18-16     18.2 bus error area  ffff_c000   ffff_d000   ffff_d6bc          ffff_c0ff  ports 0 to 3   ffff_d0ff  irc   ffff_d6bf  (note 2)  ffff_c100   ffff_d080   ffff_d6c0          ffff_c13f  (note 1)   ffff_d2ff  (note 1)   ffff_d6db  dmac  ffff_c140   ffff_d300   ffff_d6dc          ffff_c2ff  ports 5 to b   ffff_d33f  cg   ffff_d6df  (note 2)  ffff_c300   ffff_d340   ffff_d6e0          ffff_c37f  pmd   ffff_d3ff  (note 1)   ffff_d6fb  dmac  ffff_c380   ffff_d400   ffff_d6fc          ffff_c3ff  (note 1)   ffff_d4ff  modec   ffff_d6ff  (note 2)  ffff_c400   ffff_d500   ffff_d700          ffff_c43f  enc   ffff_d5ff  (note 1)   ffff_d707  dmac  ffff_c440   ffff_d600   ffff_d708          ffff_c47f  (note 1)   ffff_d61b  dmac   ffff_d70b  (note 2)  ffff_c480   ffff_d61c   ffff_d70c          ffff_c4df  sio   ffff_d61f  (note 2)   ffff_d70f  dmac  ffff_c4e0   ffff_d620   ffff_d710          ffff_c6ff  (note 1)   ffff_d63b  dmac   ffff_d7ff  (note 2)  ffff_c700   ffff_d63c   ffff_d800          ffff_c77f  tmrb   ffff_d63f  (note 2)   ffff_e3ff  (note 1)  ffff_c780   ffff_d640   ffff_e400          ffff_c82f  (note 1)   ffff_d65b  dmac   ffff_e40f  reserved  ffff_c830   ffff_d65c   ffff_e410          ffff_c83f  wdt   ffff_d65f  (note 2)   ffff_e47f  (note 1)  ffff_c840   ffff_d660   ffff_e480          ffff_c8ff  (note 1)   ffff_d67b  dmac   ffff_e48b  reserved  ffff_c900   ffff_d67c   ffff_e48c          ffff_c9ff  adc  (normal)   ffff_d67f  (note 2)   ffff_e4ff  (note 2)  ffff_ca00   ffff_d680   ffff_e500          ffff_ccff  (note 1)   ffff_d69b  dmac   ffff_e6ff  flash  /rom  ffff_cd00   ffff_d69c   ffff_e700          ffff_cdff  adc  (pmd)   ffff_d69f  (note 2)   ffff_ffff  (note 1)  ffff_ce00   ffff_d6a0         ffff_cfff  (note 1)   ffff_d6bb  dmac      note 1:  bus error area. a store access does not cause a bus error exception, but a nmi occurs.(modecr=0)  note 2:  bus error area, but a store access does not cause a nmi.  

  tmp19a71        19. electrical characteristics  the letter x in equations presented in this chapter represents the fsys or  imclk period selected by the clkprsc.prs1 or prs2 field.   19.1 maximum ratings    mask-version product    parameter  symbol  rating  unit  v cc15  (core)  -0.3 to 3.0  v cc3   (i/o)  -0.3 to 3.9  supply voltage  avcc (ad)  -0.3 to 3.6  v  input voltage  v in -0.3 to v cc3  +  0.3  (note 1) -0.3 to avcc  +  0.3  (note 2) v  per pin  i ol 15  low-level  output current  total   i ol 80  per pin  i oh -15  high-level  output current  total   i oh -50  ma  power dissipation (ta  =  85c)  pd  600  mw  10 seconds  t solder 260     soldering  temperature   3 seconds  t solder 350     average temperature  ta ave  -20 to 65     storage temperature   t stg -65 to 150      operating temperature  t opr -40 to 85       v cc 15 dvcc15  cvcc15, v cc 3  dvcc3, avcc  avccn (n  0, 1), v ss  dvss avss cvss  note 1:  the absolute maximum rating of v cc 3 (-0.3 to 3.9 v) must not be exceeded.   note 2:  since ports 5 to 7 use avcc as the power supply for each port function, the maximum rating for  a vcc (-0.3 to 3.6 v) should be applied to these ports.   note 3:  maximum ratings are limiting values of operating and environmental conditions which should not be  exceede d under the worst possible conditions. the equipment manumacturer should design so that  no maximum rating value is exceeded with respect to current, voltage, power dissipation,  temperature, etc. exposure to conditions beyond those listed above may cause permanent damage  to the device or affect device reliability, which could increase potential risks of personal injury due to  ic blowup and/or burning.        tmp19a71   19-1 

  tmp19a71            flash-version product    parameter  symbol  rating  unit  v cc2  (core)  -0.3 to 3.6  v cc3   (i/o)  -0.3 to 3.9  supply voltage  avcc (a/d)  -0.3 to3.6  v  input voltage  v in -0.3 to v cc3  +  0.3  (note 1) -0.3 to avcc  +  0.3  (note 2) v  per pin  i ol 15  low-level output  current  total   i ol 80  per pin  i oh -15  high-level output  current  total   i oh -50  ma  power dissipation (ta  =  85c)  pd  1000  mw  10 seconds  t solder 260     soldering  temperature  3 seconds  t solder 350     average temperature  ta ave  -20 to 65     storage temperature   t stg -65 to 150      other than flash  program/erase   -40 to 85  operating  temperature  flash  program/ erase  t opr -0 to 60     flash reprogram times  n we 100  cycle    v cc 2 dvcc2  cvcc2  fvcc2, v cc 3 fvcc3  dvcc3, avcc  avccn (n  0, 1),   v ss  dvss avss  cvss fvss    note 1:  the absolute maximum rating of v cc 3 (-0.3 to 3.9v) must not be exceeded.   note 2:  since ports 5 to 7 use avcc as the power supply for each port function, the maximum rating for  a vcc (-0.3 to 3.6 v) should be applied to these ports.   note 3:  maximum ratings are limiting values of operating and environmental conditions which should not be  exceede d under the worst possible conditions. the equipment manufacturer should design so that  no maximum rating value is exceeded with respect to current, voltage, power dissipation,  temperature, etc. exposure to conditions beyond those listed above may cause permanent damage  to the device or affect device reliability, which could increase potential risks of personal injury due to  ic blowup and/or burning.  note 4:  the number of times the flash memory can be reprogrammed includes programming of nonvolatile  bit s in the flash rom. note that programming nonvolatile bits to the same value is also counted in the  reprogram times.                 tmp19a71   19-2 

  tmp19a71        19.2 recommended operat ing conditions  mask-version product  ta     -40 to 85     parameter  symbol  conditions  min.  typ.  (note 1) max.  unit dvcc15   1.35   1.65  supply voltage  dvcc15  cvc c15  dvcc3  cvss dvss avss 0v   dvcc3    3.0   3.6  v  avccn  input clock = 4 to 7 mhz  fsys = 32 to 56 mhz  3.0   3.6    p0, p1, p23, p3,  p80-p83, p85, p86,  p94, pa0-pa5,  pb0-pb5  v il   3.0 v  Q  dvcc3  Q  3.6 v  0.3 dvcc3 p5-p63  (used as a port)  v il1   3.0 v  Q  avccn (n=0, 1) Q  3.6 v   0.3 avccn p20-p22, p24, p64-p67,  p70-p72, p84, p87,  p90-p93, p95, pa6,  pa7, pb6, pb7,  p95/nmi, reset     v il2   3.0 v  Q  dvcc3  Q  3.6 v  3.0 v  Q  avccn (n=0, 1) Q  3.6 v   0.2 dvcc3 (0.2 avccn) low-level input voltage  x1  v il3   1.35 v  Q  cvcc 15 Q  1.65 v  -0.3   0.1 cvcc15 v p0, p1, p23, p3,  p80-p83, p85-p86, p94,  pa0-pa5, pb0-pb5  v ih   3.0 v  Q  dvcc3  Q  3.6 v  0.7 dvcc3  dvcc3  p5-p63  (used as a port)    v ih1   3.0 v  Q  avccn (n=0, 1) Q  3.6 v   0.7 avccn  avccn  p20-p22, p24, p64-p67,  p70-p72, p84, p87,  p90-p93, p95, pa6,  pa7, pb6, pb7,  p95/nmi, reset     v ih2     3.0 v  Q  dvcc3  Q  3.6 v  3.0 v  Q  avccn (n=0, 1) Q  3.6 v   0.8 dvcc3  (0.8 avccn) dvcc3  (avccn)  high-level input voltage  x1  v ih3   1.35 v  Q  cvcc 15 Q  1.65 v  0.9 cvcc15   cvcc15  v   note 1:  recommended operating conditions are usage conditions recommended for proper operation of the device  maintaining an expected level of quality. the equipment manufacturer should design so that no recommended  operating condition is exceeded with respect to supply voltage, operating temperature range, ac/dc  specifications, etc. using the device under conditions beyond those listed above may cause the device to  malfunction.   note 2:  no maximum absolute rating as well as recommended operating condition must ever be exceeded.   note 3:  since avccn is also used as the power supply for ports 5 to 7, it should be connected to a power source even if  the  ad converter is not used.   note 4:  unless otherwise specified, the values specified for ports also apply to functions assigned to each port.        tmp19a71   19-3 

  tmp19a71          flash-version product  ta     -40 to 85     parameter  symbol  conditions  min.  typ.  (note 1) max.  unit dvcc2   2.3   2.7  supply voltage  dvcc2  fvcc2  cvcc2  dvcc3  fvcc3   cvss dvss fvss avss 0v   dvcc3    3.0   3.6  v  avccn  input clock  = 4 to 7 mhz  fsys = 32 to 56 mhz  3.0   3.6    p0, p1, p23, p3,  p80-p83, p85, p86,  p94, pa0-pa5,  pb0-pb5  v il   3.0 v  Q  dvcc3  Q  3.6 v  0.3 dvcc3 p5-p63  (used as a port)  v il1   3.0 v  Q  avccn (n=0, 1) Q  3.6 v   0.3 avccn p20-p22, p24, p64-p67,  p70-p72, p84, p87,  p90-p93, p95, pa6,  pa7, pb6, pb7,  p95/nmi, reset     v il2   3.0v  Q  dvcc3  Q  3.6 v  3.0 v  Q  avccn (n=0, 1) Q  3.6 v   0.2 dvcc3 (0.2 avccn) low-level input voltage  x1  v il3   2.3 v  Q  cvcc2  Q  2.7 v  -0.3   0.1 cvcc2 v p0, p1, p23, p3,  p80-p83, p85, p86,  p94, pa0-pa5,  pb0-pb5  v ih   3.0 v  Q  dvcc3  Q  3.6 v  0.7 dvcc3  dvcc3  p5-p63  (used as a port)    v ih1   3.0 v  Q  avccn (n=0, 1) Q  3.6 v   0.7 avccn  avccn  p20-p22, p24, p64-p67,  p70-p72, p84, p87,  p90-p93, p95, pa6,  pa7, pb6, pb7,  p95/nmi, reset     v ih2     3.0 v  Q  dvcc3  Q  3.6 v  3.0 v  Q  avccn (n=0, 1) Q  3.6 v   0.8 dvcc3  (0.8 avccn) dvcc3  (avccn)  high-level input voltage  x1  v ih3   2.3 v  Q  cvcc2  Q  2.7 v  0.9 cvcc2    cvcc2  v   note 1:  recommended operating conditions are usage conditions recommended for proper operation of the device  maintaining an expected level of quality. the equipment manufacturer should design so that no recommended  operating condition is exceeded with respect to supply voltage, operating temperature range, ac/dc  specifications, etc. using the device under conditions beyond those listed above may cause the device to  malfunction.   note 2:  no maximum absolute rating as well as recommended operating condition must ever be exceeded.   note 3:  since avccn is also used as the power supply for ports 5 to 7, it should be connected to a power source even if  the  ad converter is not used.   note 4:  unless otherwise specified, the values specified for ports also apply to functions assigned to each port.       tmp19a71   19-4 

  tmp19a71        19.3  dc electrical characteristics (1/2)  mask-version product    ta     -40 to 85     parameter  symbol  conditions  min.  typ.  (note1) max.  unit low drive  capability  i ol  =  0. 5 ma  dvcc3  R  3.0 v i ol  =  2 ma  dvcc3  R  3.0 v 0.4  low-level output  voltage  (note 2) high drive  capability  v ol   i ol  = 10  ma  dvcc3  R  3.0 v    1.0  low drive  capability  i oh  =   ? 0.5 ma   dvcc3  R  3.0 v high-level output  voltage  (note 2) high drive  capability  v oh   i oh  =   ? 2 ma  dvcc3  R  3.0 v 2.4     v input leakage current  i li   0.0 Q  v in  Q  dvcc3  0.0 Q  v in  Q  av ccn (n=0, 1)   0.02     5  output leakage current  i lo   0.2 Q  v in  Q  dvcc3 ? 0.2  0.2 Q  v in  Q  avccn ? 0.2 (n=0, 1)   0.05     10   a hysteresis (schmitt width)  p20-p22, p24, p64-p67,  p70-p72, p84, p 87, p90-p93,  p95, pa6, a7, pb6, pb7,  p95/nmi,   reset   vin  3.0v Q dvcc3 Q 3.6v  3.0 v  Q  avccn (n=0, 1) Q  3.6 v   0.4 0.9  1.6  v pull-up resistor     pup dvcc3  =  3.0  v to 3.6 v  40  100  185  k ? pin capacitance   (excluding powe r supply pins)  c io   fc  =  1 mhz     10  pf note 1:  ta  =  25 , dvcc3  =  3.3 v,  dvcc15 = 1.5v and avccn = 3.3 v, unless otherwise noted.  note 2:  the drive capability can be set to low or high in the pndssr register for each port.   flash-version product     ta   -40 to 85     parameter  symbol  conditions  min.  typ.  (note 1) max.  unit low drive  capability  i ol  =  0.5ma  dvcc3  R  3.0v   i ol  =  2ma  dvcc3  R  3.0v   0.4  low-level output  voltage  (note 2) high drive  capability  v ol   i ol  =  10 ma  dvcc3  R  3.0v      1.0  low drive  capability  i oh  =   ? 0.5ma  dvcc3  R  3.0v   high-level output  voltage  (note 2) high drive  capability  v oh   i oh  =   ? 2ma  dvcc3  R  3.0v   2.4     v input leakage current  i li   0.0 Q  v in Q  dvcc3  0.0 Q  v in  Q avccn (n=0, 1 )   0.02    5  output leakage current  i lo   0.2Q v in Q dvcc3 ? 0.2  0.2 Q  v in  Q avccn ? 0.2 (n=0,  1)   0.05    10   a hysteresis (schmitt width)  p20-p22, p24, p64-p67,  p70-p72, p84, p 87, p90-p93,  p95, pa6, pa7, pb6, pb7,  p95/nmi, reset   vin  3.0v  Q  dvcc3  Q  3.6 v  3.0 v  Q  avccn (n=0, 1) Q  3.6 v   0.4 0.9  1.6  v pull-up resistor     pup dvcc3  =  3.0  v to 3.6 v  40  100  185  k ? pin capacitance  (excluding powe r supply pins)  c io   fc  =  1 mhz     10  pf note 1:  ta = 25 , dvcc3= 3.3v, dvcc2=2.5v and avccn=3.3v, unless otherwise noted.  note 2:  the drive capability can be set to low or high in the pndssr register for each port.    tmp19a71   19-5 

  tmp19a71             19.4  dc electrical characteristics (2/2)  mask-version product  dvcc15    cvcc15  1.35 v to 1.65 v, dvcc3    3.0 v to 3.6 v, avccn    3.0 v to 3.6 v, ta    -40 to 85   (n 0, 1)    parameter  symbol  conditions  min.  typ.  (note 1) max.  (note 2) unit normal 1.5v  (note 3) i ccn15    70  90  idle (doze)  i ccd    45  60  idle (halt)  i cch   f sy s = 56 mhz   (input clock  = 7 mhz, pll x16,   gear ratio = 1/2)   45  60  ma stop  i ccst   dvcc15 = cv cc15 = 1.35 to 1.65v  dvcc3 =  3.0  to 3.6v  avccn = 3.0 to 3 .6v    3 5  ma note 1:  ta = 25 , dvcc3= 3.3v, dvcc15=1.5v and avccn=3.3v, unless otherwise noted.  note 2:  max. values are theoretical maximum values that should not be exceeded under the worst possible conditions.  note 3:  i ccn  ( typ) measurement conditions: run an arithemetic program provided by toshiba with all internal  peripheral active.     flash-version product  dvcc2    cvcc2    2.3 v to 2.7 v, dvcc3    3.0 v to 3.6 v, avccn    3.0 v to 3.6 v, ta    -40 to 85   (n    0, 1)    parameter  symbol  conditions  min.  typ.  (note 1) max.  (note 2) unit normal 2.5v  (note 3) i ccn2    212  285  idle (doze)  i ccd2    130  200  idle (halt)  i cch2   f sy s  =  56 mhz   (input clock = 7 mhz, pll x16,  gear ratio = 1/2)   120  190  ma stop  i ccst   dvcc2  =  cv cc2  =  2.3 to 2.7 v  dvcc3  =  3.0  to 3.6 v  avccn = 3.0 to  3.6 v     11 1000   a note 1:  ta = 25 , dvcc3= 3.3v, dvcc2=2.5v and avccn=3.3v, unless otherwise noted.   note 2:  max. values are theoretical maximum values that should not be exceeded under the worst possible conditions.  note 3:  i ccn   (typ) measurement conditions: run an arithmetic program provided by toshiba with all internal  peripherals acitve.       tmp19a71   19-6 

  tmp19a71          19.5  10-bit ad conversion characteristics  mask-version product  dvcc15 = cvcc15 = 1.35 to 1.65 v, dvcc3 = 3.0 to 3.6 v, avccn = vrefh = 3.0 to 3.6 v,   avss = dvss = vrefl = 0 v, ta    -40 to 85       parameter  symbol  conditions  min  typ  max  unit analog reference voltage (+)  (note 3) vrefh   3.0    3.6  v  analog input voltage  vain    avss    avccn  v  integral nonlinearity error  (note 6) ?      1.5    3  lsb differential nonlinearity error  ?      1    2  lsb offset error  ?      4    7  lsb gain error  ?      2    4  lsb relative error  (note 5) ?   4  8  lsb total error  ?  avccn   =  vrefh =   3.0 t o 3.6 v  dvss = avss  avccn load capacitance  R  10   f  vrefh load capacitance  R  10   f  conversion time  R  2.36   s       4    7  lsb note 1:  1 lsb  =  (vrefh ? vrefl)/1024 [v]  note 2:  the supply current flowing through the avccn pin is included in the digital supply current parameter (i cc ).   note 3:  the vrefhn pin is shared with the avccn pin.  note 4:   the above characteristics apply when the adc input pins are not used for other functions.   note 5:   indicates the difference between the minimum and maximum conversion errors.   note 6:  indicates a value after offset and gain errors have been adjusted.      tmp19a71   19-7 

  tmp19a71            flash-version product  dvcc2 = fvcc2 = cvcc2 = 2.5 0.2 v, dvcc3 = 3.3 0.3 v, avccn = vrefh = 3.0 to 3.6 v,  avss = dvss = vrefl = 0 v, ta    -40 to 85       parameter  symbol  condition  min  typ  max  unit analog reference voltage (+)  (note 3) vrefh   3.0    3.6  v  analog input voltage  vain    avss    avccn  v  integral nonlinearity error  (note 6) ?      1.5    3  lsb differential nonlinearity error   ?      1    2  lsb offset error  ?      4    7  lsb gain error  ?      2    4  lsb relative error  (note 6) ?   4  8  lsb total error  ?  avccn   =  vrefh = 3.0  to 3.6v  dvss = avss  avccn load capacitance  R 10  f  vrefh load capacitance  R 10  f  conversion time R 2.36  s        4    7  lsb note 1:  1 lsb  =  (vrefh ? vrefl)/1024 [v]  note 2:  the supply current flowing through the avccn pin is included in the digital supply current parameter (i cc ).  note 3:  the vrefhn pin is shared with the avccn pin.   note 4:  the above characteristics apply when the adc input pins are not used for other functions.   note 5:   indicates the difference between the minimum and maximum conversion errors.   note 6:   indicates a value after offset and gain errors have been adjusted.       tmp19a71   19-8 

  tmp19a71        19.6 sio timings  mask-version product     (1) i/o interface mode (dvcc3 = 3.3 0.3 v, dvcc15 = 1.5 0.15 v, ta = -40 to 85 c)  the letter x in the tables below represents the system clock fsys period which depends on the clock  gea r setting.     ?    sclk input mode (sio2)  equation 56  mhz  parameter  symbol min max min  max  unit  sclk period  t scy 16x   286    ns  txd data to sclk rise or fall *  t oss (tscy/2) - 4x - 23   50    ns  txd data hold after sclk rise or fall*  t ohs (tscy/2) + 2x    179     ns  rxd data valid to sclk rise or fall*  t srd 2x + 8    44    ns  rxd data hold after sclk rise or fall*  t hsr 0    0   ns  *) sclk rise or fall: measured relative to the programmed active edge of sclk.    ?   sclk output mode (sio2)  equation 56  mhz  parameter  symbol min  max  min  max  unit  sclk period (programmable)  t scy 16x   286    ns  txd data to sclk rise  t oss (tscy/2) - 15    128    ns  txd data hold after sclk rise  t ohs (tscy/2) - 15    128    ns  rxd data valid to sclk rise  t srd 2x + 23    59    ns  rxd data hold after sclk rise   t hsr 0   0    ns    output data  txd  input data  rxd  sclk  output mode  a ctive-high  0  valid  t oss   t scy   t ohs 1 2 3  t srd   t hsr 0  1 2 3  valid valid valid sclk  input mode  a ctive-low      note 1: output level measurement conditions: high 0.8dvcc3 [v] / low 0.2dvcc3 [v], cl=30 pf  note 2: input level measurement conditio n s: high 0.7dvcc3 [v] / low 0.2dvcc3 [v]          tmp19a71   19-9 

  tmp19a71          flash-version product  (1) i/o interface mode (dvcc3 = 3.3 0.3 v,  dvcc2 = 2.5 0.2 v, ta = -40 to 85 oc)  the letter x in the tables below represents the system clock fsys period which depends on the clock  gea r setting.     ?   sclk input mode (sio2)  equation 56  mhz  parameter  symbol min max min  max  unit  sclk period  t scy 16x   286    ns  txd data to sclk rise or fall*  t oss (tscy/2) - 4x - 23   50    ns  txd data hold after sclk rise or fall*  t ohs (tscy/2) + 2x    179     ns  rxd data valid to sclk rise or fall*  t srd 2x + 8    44    ns  rxd data hold after sclk rise or fall*  t hsr 0   0    ns  *) sclk rise or fall: measured relative to the programmed active edge of sclk    ?   sclk output mode (sio2)  equation 56  mhz  parameter  symbol min  max  min  max  unit  sclk period (programmable)  t scy 16x   286    ns  txd data to sclk rise  t oss (tscy/2) ? 15   128   ns  txd data hold after sclk rise  t ohs (tscy/2) ? 15   128   ns  rxd data valid to sclk rise  t srd 2x + 23    59   ns  rxd data hold after sclk rise  t hsr 0    0   ns    output data  txd  input data  rxd  sclk  output mode  a ctive-high  0  valid  t oss   t scy   t ohs 1 2 3  t srd   t hsr 0  1 2 3  valid valid valid sclk  input mode  a ctive-low      note 1: output level measurement conditions: high 0.8dvcc3 [v] / low 0.2dvcc3 [v], cl=30 pf  note 2: input level measurement conditio n s: high 0.7dvcc3 [v] / low 0.2dvcc3 [v]      tmp19a71   19-10 

  tmp19a71        19.7 event counter  mask-version and flash-version products  the letter x in the table below represents the imclk period.   equation  imclk = 28 mhz  parameter  symbol  min  max  min  max  unit  clock low-level pulse width  t vckl x  +  100  136   ns  clock high-level pulse width  t vckh x  +  100  136   ns    19.8 capture  mask-version and flash-version products  the letter x in the table below represents the imclk period.   equation  imclk = 28 mhz  parameter  symbol  min  max  min  max  unit  low-level pulse width  t cpl x  +  100  136   ns  high-level pulse width  t cph x  +  100  136   ns    19.9 interrupts (intc)  mask-version and flash-version products  the letter x in the table below repres ents the system clock fsys period.   equation  fsys = 56 mhz  parameter  symbol  min  max  min  max  unit  int0 to a low-level pulse width  t intal x  +  100  118   ns  int0 to a high-level pulse width  t intah x  +  100  118   ns    19.10 interrupts (nmi, stop wakeup interrupt)  mask-version and flash-version products  equation  fsys = 56 mhz  parameter  symbol  min  max  min  max  unit  nmi, int0 to 4 low-level pulse width  t intbl 100   100    ns  int0 to 4 high-level pulse width  t intbh 100   100    ns      tmp19a71   19-11 

  tmp19a71            19.11 adtrg input  mask-version and flash-version products  the letter x in the table below represents the imclk period.   equation  imclk = 28 mhz  parameter  symbol  min  max  min  max  unit  adtrg low-level pulse width  tad l x  +  100  136   ns  adtrg high-level pulse width  tadh  x  +   100  136   ns          tmp19a71   19-12 

  tmp19a71        20.  package dimensions  20.1 p-lqfp-1414-0.50f               tmp19a71   20-1 

  tmp19a71            20.2 p-qfp-1420-0.65a      tmp19a71   20-2